Datasheet

4.6.2.3. Double Buffering
Figure 106 shows how a change in input value will produce a change in output duty cycle. This can be used to
approximate some analog waveform such as a sine wave.
TOP
Count
IOVDD
TOP/3
2×TOP/3
V
Input (Count)
Counter compare level
Counter
0
T 2T 3T
t
Output (Pulse)
GPIO pulse output
0
T 5T/3T/3 2T 3T
t
Figure 106. The input
value varies with each
counter period: first
TOP / 3, then 2 × TOP
/ 3, and finally TOP + 1
for 100% duty cycle.
Each increase in the
input value causes a
corresponding
increase in the output
duty cycle.
In Figure 106, the input value only changes at the instant where the counter wraps through 0. Figure 107 shows what
happens if the input value is allowed to change at any other time: an unwanted glitch is produced at the output.
TOP
Count
IOVDD
TOP/3
2×TOP/3
V
Input (Count)
Counter compare level
Counter
0
T 2T 3T
t
Output (Pulse)
GPIO pulse output
0
T 5T/3T/3 2T 3T
t
Figure 107. The input
value changes whilst
the counter is mid-
ramp. This produces
additional toggling at
the output.
The behaviour becomes even more perplexing if the TOP register is also modified. It would be difficult for software to write
to CC or TOP with the correct timing. To solve this, each slice has two copies of the CC and TOP registers: one copy which
software can modify, and another, internal copy which is updated from the first register at the instant the counter wraps.
Software can modify its copy of the register at will, but the changes are not captured by the PWM output until the next
wrap.
Figure 108 shows the sequence of events where a software interrupt handler changes the value of CC_A each time the
counter wraps.
RP2040 Datasheet
4.6. PWM 549