Datasheet

Bits Name Description Type Reset
3 ROE Sticky flag indicating the RX FIFO was read when empty.
This read was ignored by the FIFO.
WC 0x0
2 WOF Sticky flag indicating the TX FIFO was written when full.
This write was ignored by the FIFO.
WC 0x0
1 RDY Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is
ready for more data)
RO 0x1
0 VLD Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD
is valid)
RO 0x0
FIFO_WR Register
Description
Write access to this core’s TX FIFO
Table 36. FIFO_WR
Register
Bits Name Description Type Reset
31:0 NONAME WF 0x00000000
FIFO_RD Register
Description
Read access to this core’s RX FIFO
Table 37. FIFO_RD
Register
Bits Name Description Type Reset
31:0 NONAME RF -
SPINLOCK_ST Register
Description
Spinlock state
A bitmap containing the state of all 32 spinlocks (1=locked).
Mainly intended for debugging.
Table 38.
SPINLOCK_ST
Register
Bits Name Description Type Reset
31:0 NONAME RO 0x00000000
DIV_UDIVIDEND Register
Description
Divider unsigned dividend
Write to the DIVIDEND operand of the divider, i.e. the p in p / q.
Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an
unsigned calculation, and the S alias starts a signed calculation.
Table 39.
DIV_UDIVIDEND
Register
Bits Name Description Type Reset
31:0 NONAME RW 0x00000000
DIV_UDIVISOR Register
RP2040 Datasheet
2.3. Processor subsystem 54