Datasheet

4.6.1. Overview
Pulse width modulation (PWM) is a scheme where a digital signal provides a smoothly varying average voltage. This is
achieved with positive pulses of some controlled width, at regular intervals. The fraction of time spent high is known as
the duty cycle. This may be used to approximate an analog output, or control switchmode power electronics.
The RP2040 PWM block has 8 identical slices. Each slice can drive two PWM output signals, or measure the frequency or
duty cycle of an input signal. This gives a total of up to 16 controllable PWM outputs. All 30 GPIO pins can be driven by the
PWM block.
Output
(pin A)
IRQ
Outout compare unit
(level A)
Output
(pin B)
Outout compare unit
(level B)
Fractional Clock
Divider (8.4)
Rising edge
Input
(pin B)
Event select
1
Falling edge
IRQ Latch
up/down Counter
16b, programmable
wrap
Phase
Advance
Phase
Retard
Wrap
ENEN
Figure 101. A single
PWM slice. A 16-bit
counter counts from 0
up to some
programmed value,
and then wraps to
zero, or counts back
down again,
depending on PWM
mode. The A and B
outputs transition high
and low based on the
current count value
and the
preprogrammed A and
B thresholds. The
counter advances
based on a number of
events: it may be free-
running, or gated by
level or edge of an
input signal on the B
pin. A fractional
divider slows the
overall count rate for
finer control of output
frequency.
Each PWM slice is equipped with the following:
•
16-bit counter
•
8.4 fractional clock divider
•
Two independent output channels, duty cycle from 0% to 100% inclusive
•
Dual slope and trailing edge modulation
•
Edge-sensitive input mode for frequency measurement
•
Level-sensitive input mode for duty cycle measurement
•
Configurable counter wrap value
◦
Wrap and level registers are double buffered and can be changed race-free while PWM is running
•
Interrupt request and DMA request on counter wrap
•
Phase can be precisely advanced or retarded while running (increments of one count)
Slices can be enabled or disabled simultaneously via a single, global control register. The slices then run in perfect
lockstep, so that more complex power circuitry can be switched by the outputs of multiple slices.
4.6.2. Programmer’s Model
All 30 GPIO pins on RP2040 can be used for PWM:
Table 543. Mapping of
PWM channels to
GPIO pins on RP2040.
This is also shown in
the main GPIO
function table, Table
274
GPIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PWM Channel 0A 0B 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B 7A 7B
GPIO 16 17 18 19 20 21 22 23 24 25 26 27 28 29
PWM Channel 0A 0B 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B
•
The 16 PWM channels (8 2-channel slices) appear on GPIO0 to GPIO15, in the order PWM0 A, PWM0 B, PWM1 A…
•
This repeats for GPIO16 to GPIO29. GPIO16 is PWM0 A, GPIO17 is PWM0 B, so on up to PWM6 B on GPIO29
•
The same PWM output can be selected on two GPIO pins; the same signal will appear on each GPIO.
RP2040 Datasheet
4.6. PWM 546