Datasheet

Table Of Contents
SSPPERIPHID3 Register
Description
Peripheral identification registers, SSPPeriphID0-3 on page 3-13
Table 538.
SSPPERIPHID3
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 CONFIGURATION These bits read back as 0x00 RO 0x00
SSPPCELLID0 Register
Description
PrimeCell identification registers, SSPPCellID0-3 on page 3-16
Table 539.
SSPPCELLID0 Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 SSPPCELLID0 These bits read back as 0x0D RO 0x0d
SSPPCELLID1 Register
Description
PrimeCell identification registers, SSPPCellID0-3 on page 3-16
Table 540.
SSPPCELLID1 Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 SSPPCELLID1 These bits read back as 0xF0 RO 0xf0
SSPPCELLID2 Register
Description
PrimeCell identification registers, SSPPCellID0-3 on page 3-16
Table 541.
SSPPCELLID2 Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 SSPPCELLID2 These bits read back as 0x05 RO 0x05
SSPPCELLID3 Register
Description
PrimeCell identification registers, SSPPCellID0-3 on page 3-16
Table 542.
SSPPCELLID3 Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 SSPPCELLID3 These bits read back as 0xB1 RO 0xb1
4.6. PWM
RP2040 Datasheet
4.6. PWM 545