Datasheet

Table Of Contents
Description
Interrupt clear register, SSPICR on page 3-11
Table 533. SSPICR
Register
Bits Name Description Type Reset
31:2 Reserved. - - -
1 RTIC Clears the SSPRTINTR interrupt WC 0x0
0 RORIC Clears the SSPRORINTR interrupt WC 0x0
SSPDMACR Register
Description
DMA control register, SSPDMACR on page 3-12
Table 534. SSPDMACR
Register
Bits Name Description Type Reset
31:2 Reserved. - - -
1 TXDMAE Transmit DMA Enable. If this bit is set to 1, DMA for the
transmit FIFO is enabled.
RW 0x0
0 RXDMAE Receive DMA Enable. If this bit is set to 1, DMA for the
receive FIFO is enabled.
RW 0x0
SSPPERIPHID0 Register
Description
Peripheral identification registers, SSPPeriphID0-3 on page 3-13
Table 535.
SSPPERIPHID0
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 PARTNUMBER0 These bits read back as 0x22 RO 0x22
SSPPERIPHID1 Register
Description
Peripheral identification registers, SSPPeriphID0-3 on page 3-13
Table 536.
SSPPERIPHID1
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:4 DESIGNER0 These bits read back as 0x1 RO 0x1
3:0 PARTNUMBER1 These bits read back as 0x0 RO 0x0
SSPPERIPHID2 Register
Description
Peripheral identification registers, SSPPeriphID0-3 on page 3-13
Table 537.
SSPPERIPHID2
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:4 REVISION These bits return the peripheral revision RO 0x3
3:0 DESIGNER1 These bits read back as 0x4 RO 0x4
RP2040 Datasheet
4.5. SPI 544