Datasheet

Bits Name Description Type Reset
3 TXIM Transmit FIFO interrupt mask: 0 Transmit FIFO half empty
or less condition interrupt is masked. 1 Transmit FIFO half
empty or less condition interrupt is not masked.
RW 0x0
2 RXIM Receive FIFO interrupt mask: 0 Receive FIFO half full or less
condition interrupt is masked. 1 Receive FIFO half full or
less condition interrupt is not masked.
RW 0x0
1 RTIM Receive timeout interrupt mask: 0 Receive FIFO not empty
and no read prior to timeout period interrupt is masked. 1
Receive FIFO not empty and no read prior to timeout period
interrupt is not masked.
RW 0x0
0 RORIM Receive overrun interrupt mask: 0 Receive FIFO written to
while full condition interrupt is masked. 1 Receive FIFO
written to while full condition interrupt is not masked.
RW 0x0
SSPRIS Register
Description
Raw interrupt status register, SSPRIS on page 3-10
Table 531. SSPRIS
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
3 TXRIS Gives the raw interrupt state, prior to masking, of the
SSPTXINTR interrupt
RO 0x1
2 RXRIS Gives the raw interrupt state, prior to masking, of the
SSPRXINTR interrupt
RO 0x0
1 RTRIS Gives the raw interrupt state, prior to masking, of the
SSPRTINTR interrupt
RO 0x0
0 RORRIS Gives the raw interrupt state, prior to masking, of the
SSPRORINTR interrupt
RO 0x0
SSPMIS Register
Description
Masked interrupt status register, SSPMIS on page 3-11
Table 532. SSPMIS
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
3 TXMIS Gives the transmit FIFO masked interrupt state, after
masking, of the SSPTXINTR interrupt
RO 0x0
2 RXMIS Gives the receive FIFO masked interrupt state, after
masking, of the SSPRXINTR interrupt
RO 0x0
1 RTMIS Gives the receive timeout masked interrupt state, after
masking, of the SSPRTINTR interrupt
RO 0x0
0 RORMIS Gives the receive over run masked interrupt status, after
masking, of the SSPRORINTR interrupt
RO 0x0
SSPICR Register
RP2040 Datasheet
4.5. SPI 543