Datasheet

Table Of Contents
SSPDR Register
Description
Data register, SSPDR on page 3-6
Table 527. SSPDR
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15:0 DATA Transmit/Receive FIFO: Read Receive FIFO. Write Transmit
FIFO. You must right-justify data when the PrimeCell SSP is
programmed for a data size that is less than 16 bits.
Unused bits at the top are ignored by transmit logic. The
receive logic automatically right-justifies.
RWF -
SSPSR Register
Description
Status register, SSPSR on page 3-7
Table 528. SSPSR
Register
Bits Name Description Type Reset
31:5 Reserved. - - -
4 BSY PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is
currently transmitting and/or receiving a frame or the
transmit FIFO is not empty.
RO 0x0
3 RFF Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
FIFO is full.
RO 0x0
2 RNE Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1
Receive FIFO is not empty.
RO 0x0
1 TNF Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1
Transmit FIFO is not full.
RO 0x1
0 TFE Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
Transmit FIFO is empty.
RO 0x1
SSPCPSR Register
Description
Clock prescale register, SSPCPSR on page 3-8
Table 529. SSPCPSR
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 CPSDVSR Clock prescale divisor. Must be an even number from 2-
254, depending on the frequency of SSPCLK. The least
significant bit always returns zero on reads.
RW 0x00
SSPIMSC Register
Description
Interrupt mask set or clear register, SSPIMSC on page 3-9
Table 530. SSPIMSC
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
RP2040 Datasheet
4.5. SPI 542