Datasheet

Table 31. GPIO_HI_OE
Register
Bits Name Description Type Reset
31:6 Reserved. - - -
5:0 NONAME Set output enable (1/0 -> output/input) for QSPI IO0…5.
Reading back gives the last value written.
If core 0 and core 1 both write to GPIO_HI_OE
simultaneously (or to a SET/CLR/XOR alias),
the result is as though the write from core 0 took place
first,
and the write from core 1 was then applied to that
intermediate result.
RW 0x00
GPIO_HI_OE_SET Register
Description
QSPI output enable set
Table 32.
GPIO_HI_OE_SET
Register
Bits Name Description Type Reset
31:6 Reserved. - - -
5:0 NONAME
Perform an atomic bit-set on GPIO_HI_OE, i.e. GPIO_HI_OE |=
wdata
RW 0x00
GPIO_HI_OE_CLR Register
Description
QSPI output enable clear
Table 33.
GPIO_HI_OE_CLR
Register
Bits Name Description Type Reset
31:6 Reserved. - - -
5:0 NONAME
Perform an atomic bit-clear on GPIO_HI_OE, i.e. GPIO_HI_OE
&= ~wdata
RW 0x00
GPIO_HI_OE_XOR Register
Description
QSPI output enable XOR
Table 34.
GPIO_HI_OE_XOR
Register
Bits Name Description Type Reset
31:6 Reserved. - - -
5:0 NONAME Perform an atomic bitwise XOR on GPIO_HI_OE, i.e.
GPIO_HI_OE ^= wdata
RW 0x00
FIFO_ST Register
Description
Status register for inter-core FIFOs (mailboxes).
There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0.
Both are 32 bits wide and 8 words deep.
Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
Table 35. FIFO_ST
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
RP2040 Datasheet
2.3. Processor subsystem 53