Datasheet


NOTE
In Figure 91, Q is an undefined signal.
SSPCLKOUT/SSPCLIN
SSPFSSOUT/SSPFSSIN
SSPTXD/SSPRXD
nSSPOE (=0)
MSBLSB LSB MSB
4 to 16 bits
Figure 92. Motorola
SPI frame format,
continuous transfer,
with SPO=1 and
SPH=0
In this configuration, during idle periods:
•
the SSPCLKOUT signal is forced HIGH
•
the SSPFSSOUT signal is forced HIGH
•
the transmit data line SSPTXD is arbitrarily forced LOW
•
the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance
•
when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW, enabling the SSPCLKOUT
pad, active-LOW enable
•
when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH, disabling the SSPCLKOUT pad,
active-LOW enable.
If the PrimeCell SSP is enabled, and there is valid data within the transmit FIFO, the start of transmission is signified by the
SSPFSSOUT master signal being driven LOW, and this causes slave data to be immediately transferred onto the SSPRXD
line of the master. The nSSPOE line is driven LOW, enabling the master SSPTXD output pad.
One half period later, valid master data is transferred to the SSPTXD line. Now that both the master and slave data have
been set, the SSPCLKOUT master clock pin becomes LOW after one additional half SSPCLKOUT period. This means that
data is captured on the falling edges and be propagated on the rising edges of the SSPCLKOUT signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSPFSSOUT line is returned to
its idle HIGH state one SSPCLKOUT period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSPFSSOUT signal must be pulsed HIGH between
each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not
permit it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSPFSSIN pin of the slave
device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the
SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period after the last bit has been captured.
4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
Figure 93 shows the transfer signal sequence for Motorola SPI format with SPO=1, SPH=1, and it covers both single and
continuous transfers.
SSPCLKOUT/SSPCLIN
SSPFSSOUT/SSPFSSIN
SSPRXD
MSB LSBQ Q
SSPRXD
MSB LSB
4 to 16 bits
nSSPOE
Figure 93. Motorola
SPI frame format with
SPO=1 and SPH=1,
single and continuous
transfers
RP2040 Datasheet
4.5. SPI 535