Datasheet

4.5.3.9.2. SPH, clock phase
The SPH control bit selects the clock edge that captures data and enables it to change state. It has the most impact on
the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge.
When the SPH phase control bit is LOW, data is captured on the first clock edge transition.
When the SPH clock phase control bit is HIGH, data is captured on the second clock edge transition.
4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
Figure 88 and Figure 89 shows a continuous transmission signal sequence for Motorola SPI frame format with SPO=0,
SPH=0. Figure 88 shows a single transmission signal sequence for Motorola SPI frame format with SPO=0, SPH=0.
SSPCLKOUT/SSPCLIN
SSPFSSOUT/SSPFSSIN
SSPRXD
MSB LSB Q
SSPRXD
MSB LSB
4 to 16 bits
nSSPOE
Figure 88. Motorola
SPI frame format,
single transfer, with
SPO=0 and SPH=0
Figure 89 shows a continuous transmission signal sequence for Motorola SPI frame format with SPO=0, SPH=0.
SSPCLKOUT/SSPCLIN
SSPFSSOUT/SSPFSSIN
SSPTXD/SSPRXD
nSSPOE (=0)
MSBLSB LSB MSB
4 to 16 bits
Figure 89. Motorola
SPI frame format,
single transfer, with
SPO=0 and SPH=0
In this configuration, during idle periods:
•
the SSPCLKOUT signal is forced LOW
•
the SSPFSSOUT signal is forced HIGH
•
the transmit data line SSPTXD is arbitrarily forced LOW
•
the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance
•
when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW, enabling the SSPCLKOUT
pad, active-LOW enable
•
when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH, disabling the SSPCLKOUT pad,
active-LOW enable.
If the PrimeCell SSP is enable, and there is valid data within the transmit FIFO, the start of transmission is signified by the
SSPFSSOUT master signal being driven LOW. This causes slave data to be enabled onto the SSPRXD input line of the
master. The nSSPOE line is driven LOW, enabling the master SSPTXD output pad.
One-half SSPCLKOUT period later, valid master data is transferred to the SSPTXD pin. Now that both the master and slave
data have been set, the SSPCLKOUT master clock pin goes HIGH after one additional half SSPCLKOUT period.
The data is now captured on the rising and propagated on the falling edges of the SSPCLKOUT signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the SSPFSSOUT line is
returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSPFSSOUT signal must be pulsed HIGH between
each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not
permit it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSPFSSIN pin of the slave
device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the
RP2040 Datasheet
4.5. SPI 533