Datasheet

PRESETn
PSEL
PENABLE
PWRITE
PADDR[11:2]
PWDATA[15:0]
PRDATA[15:0]
PCLK
AMBA
APB
interface
FIFO status
and interrupt
generation
Transmit and
receive logic
PWDATAIn[15:0] SSPTXINTR
TxRdDataIn[15:0]
SSPRXINTR
SSPRORINTR
SSPRTINTR
PCLK
SSPTXINTR
SSPRXDMACLR
SSPTXDMACLR
SSPRXDMASREQ
SSPRXDMABREQ
SSPTXDMASREQ
SSPTXDMABREQ
RxFRdData
[15:0]
nSSPRST
PCLK
SSPCLKDIV
RxWrData[15:0]
Prescale value
Tx/Rx FIFO watermark levels
Tx/Rx params
SSPCLK
nSSPOE
SSPTXD
SSPFSSOUT
SSPCLKOUT
nSSPCTLOE
SSPCLKIN
SSPFSSIN
SSPRXD
SSPRTRINTR
SSPRORINTR
SSPRXRINTR
SSPINTR
PCLK
PCLK
Tx FIFO
16 bits wide,
8 locations
deep
Rx FIFO
16 bits wide,
8 locations
deep
Clock
prescaler
Register
block
DMA
interface
SSPCLK
SSPCLK
DATAOUTDATAIN
Figure 85. PrimeCell
SSP block diagram.
For clarity, does not
show the test logic.
4.5.2.1. AMBA APB interface
The AMBA APB interface generates read and write decodes for accesses to status and control registers, and transmit and
receive FIFO memories.
4.5.2.2. Register block
The register block stores data written, or to be read, across the AMBA APB interface.
4.5.2.3. Clock prescaler
When configured as a master, an internal prescaler, comprising two free-running reloadable serially linked counters,
provides the serial output clock SSPCLKOUT.
You can program the clock prescaler, using the SSPCPSR register, to divide SSPCLK by a factor of 2-254 in steps of two.
By not utilizing the least significant bit of the SSPCPSR register, division by an odd number is not possible which ensures
that a symmetrical, equal mark space ratio, clock is generated. See SSPCPSR.
The output of the prescaler is divided again by a factor of 1-256, by programming the SSPCR0 control register, to give the
final master output clock SSPCLKOUT.
4.5.2.4. Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep memory buffer. CPU data written across the AMBA APB
interface are stored in the buffer until read out by the transmit logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion, and
transmission to the attached slave or master respectively, through the SSPTXD pin.
4.5.2.5. Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep memory buffer. Received data from the serial interface are
stored in the buffer until read out by the CPU across the AMBA APB interface.
RP2040 Datasheet
4.5. SPI 528