Datasheet

Each controller can be connected to a number of GPIO pins as defined in the GPIO muxing Table 274 in Section 2.18.2.
Connections to the GPIO muxing are prefixed with the SPI instance name spi0_ or spi1_, and include the following:
•
clock sclk (referred to as SSPCLKOUT in the following sections)
•
active low chip select or frame sync ss_n (referred to as SSPFSSOUT in the following sections)
•
transmit data tx (referred to as SSPTXD in the following sections)
•
receive data rd (referred to as SSPRXD in the following sections)
The SPI uses clk_peri as its reference clock for SPI timing, and is referred to as SSPCLK in the following sections. clk_sys
is used as the bus clock, and is referred to as PCLK in the following sections (also see Figure 26).
4.5.1. Overview
The PrimeCell SSP is a master or slave interface for synchronous serial communication with peripheral devices that have
Motorola SPI, National Semiconductor Microwire, or Texas Instruments synchronous serial interfaces.
The PrimeCell SSP performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses
data, control, and status information through the AMBA APB interface. The transmit and receive paths are buffered with
internal FIFO memories enabling up to eight 16-bit values to be stored independently in both transmit and receive modes.
Serial data is transmitted on SSPTXD and received on SSPRXD.
The PrimeCell SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock,
SSPCLKOUT, from the input clock, SSPCLK. Bit rates are supported to 2MHz and higher, subject to choice of frequency
for SSPCLK, and the maximum bit rate is determined by peripheral devices.
You can use the control registers SSPCR0 and SSPCR1 to program the PrimeCell SSP operating mode, frame format, and
size.
The following individually maskable interrupts are generated:
•
SSPTXINTR requests servicing of the transmit buffer
•
SSPRXINTR requests servicing of the receive buffer
•
SSPRORINTR indicates an overrun condition in the receive FIFO
•
SSPRTINTR indicates that a timeout period expired while data was present in the receive FIFO.
A single combined interrupt is asserted if any of the individual interrupts are asserted and unmasked. This interrupt is
connected to the processor interrupt controllers in RP2040.
In addition to the above interrupts, a set of DMA signals are provided for interfacing with a DMA controller.
Depending on the operating mode selected, the SSPFSSOUT output operates as:
•
an active-HIGH frame synchronization output for Texas Instruments synchronous serial frame format
•
an active-LOW slave select for SPI and Microwire.
4.5.2. Functional Description
RP2040 Datasheet
4.5. SPI 527