Datasheet

Bits Name Description Type Reset
1 SLV_DISABLED_W
HILE_BUSY
Slave Disabled While Busy (Transmit, Receive). This bit
indicates if a potential or active Slave operation has been
aborted due to the setting bit 0 of the IC_ENABLE register
from 1 to 0. This bit is set when the CPU writes a 0 to the
IC_ENABLE register while:
(a) DW_apb_i2c is receiving the address byte of the Slave-
Transmitter operation from a remote master;
OR,
(b) address and data bytes of the Slave-Receiver operation
from a remote master.
When read as 1, DW_apb_i2c is deemed to have forced a
NACK during any part of an I2C transfer, irrespective of
whether the I2C address matches the slave address set in
DW_apb_i2c (IC_SAR register) OR if the transfer is
completed before IC_ENABLE is set to 0 but has not taken
effect.
Note: If the remote I2C master terminates the transfer with
a STOP condition before the DW_apb_i2c has a chance to
NACK a transfer, and IC_ENABLE[0] has been set to 0, then
this bit will also be set to 1.
When read as 0, DW_apb_i2c is deemed to have been
disabled when there is master activity, or when the I2C bus
is idle.
Note: The CPU can safely read this bit when IC_EN (bit 0) is
read as 0.
Reset value: 0x0
0x0 -> Slave is disabled when it is idle
0x1 -> Slave is disabled when it is active
RO 0x0
0 IC_EN ic_en Status. This bit always reflects the value driven on the
output port ic_en. - When read as 1, DW_apb_i2c is deemed
to be in an enabled state. - When read as 0, DW_apb_i2c is
deemed completely inactive. Note: The CPU can safely
read this bit anytime. When this bit is read as 0, the CPU
can safely read SLV_RX_DATA_LOST (bit 2) and
SLV_DISABLED_WHILE_BUSY (bit 1).
Reset value: 0x0
0x0 -> I2C disabled
0x1 -> I2C enabled
RO 0x0
IC_FS_SPKLEN Register
Description
I2C SS, FS or FM+ spike suppression limit
This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike
RP2040 Datasheet
4.4. I2C 524