Datasheet

Table Of Contents
Table 515.
IC_SDA_SETUP
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 SDA_SETUP SDA Setup. It is recommended that if the required delay is
1000ns, then for an ic_clk frequency of 10 MHz,
IC_SDA_SETUP should be programmed to a value of 11.
IC_SDA_SETUP must be programmed with a minimum
value of 2.
RW 0x64
IC_ACK_GENERAL_CALL Register
Description
I2C ACK General Call Register
The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.
This register is applicable only when the DW_apb_i2c is in slave mode.
Table 516.
IC_ACK_GENERAL_CA
LL Register
Bits Name Description Type Reset
31:1 Reserved. - - -
0 ACK_GEN_CALL ACK General Call. When set to 1, DW_apb_i2c responds
with a ACK (by asserting ic_data_oe) when it receives a
General Call. Otherwise, DW_apb_i2c responds with a
NACK (by negating ic_data_oe).
0x0 -> Generate NACK for a General Call
0x1 -> Generate ACK for a General Call
RW 0x1
IC_ENABLE_STATUS Register
Description
I2C Enable Status Register
The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is,
when DW_apb_i2c is disabled.
If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.
If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.
Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c
depends on I2C bus activities.
Table 517.
IC_ENABLE_STATUS
Register
Bits Name Description Type Reset
31:3 Reserved. - - -
RP2040 Datasheet
4.4. I2C 522