Datasheet

Table Of Contents
Table 513.
IC_DMA_TDLR
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
3:0 DMATDL Transmit Data Level. This bit field controls the level at
which a DMA request is made by the transmit logic. It is
equal to the watermark level; that is, the dma_tx_req signal
is generated when the number of valid data entries in the
transmit FIFO is equal to or below this field value, and
TDMAE = 1.
Reset value: 0x0
RW 0x0
IC_DMA_RDLR Register
Description
I2C Receive Data Level Register
Table 514.
IC_DMA_RDLR
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
3:0 DMARDL Receive Data Level. This bit field controls the level at which
a DMA request is made by the receive logic. The watermark
level = DMARDL+1; that is, dma_rx_req is generated when
the number of valid data entries in the receive FIFO is equal
to or more than this field value + 1, and RDMAE =1. For
instance, when DMARDL is 0, then dma_rx_req is asserted
when 1 or more data entries are present in the receive
FIFO.
Reset value: 0x0
RW 0x0
IC_SDA_SETUP Register
Description
I2C SDA Setup Register
This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge
of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The
relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed
with a value equal to or greater than 2.
Writes to this register succeed only when IC_ENABLE[0] = 0.
Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk
periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c
when operating as a slave transmitter.
RP2040 Datasheet
4.4. I2C 521