Datasheet

IC_TX_ABRT_SOURCE Register
Description
I2C Transmit Abort Source Register
This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the
IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT
must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the
GC_OR_START bit must be cleared (IC_TAR[10]).
Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in
this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for
one cycle and is then re-asserted.
Table 510.
IC_TX_ABRT_SOURCE
Register
Bits Name Description Type Reset
31:23 TX_FLUSH_CNT This field indicates the number of Tx FIFO Data Commands
which are flushed due to TX_ABRT interrupt. It is cleared
whenever I2C is disabled.
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter or Slave-
Transmitter
RO 0x000
22:17 Reserved. - - -
16 ABRT_USER_ABR
T
This is a master-mode-only bit. Master has detected the
transfer abort (IC_ENABLE[1])
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter
0x0 -> Transfer abort detected by master- scenario not
present
0x1 -> Transfer abort detected by master
RO 0x0
15 ABRT_SLVRD_INT
X
1: When the processor side responds to a slave mode
request for data to be transmitted to a remote master and
user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.
Reset value: 0x0
Role of DW_apb_i2c: Slave-Transmitter
0x0 -> Slave trying to transmit to remote master in read
mode- scenario not present
0x1 -> Slave trying to transmit to remote master in read
mode
RO 0x0
RP2040 Datasheet
4.4. I2C 515