Datasheet

Table Of Contents
Bits Name Description Type Reset
5 MST_ACTIVITY Master FSM Activity Status. When the Master Finite State
Machine (FSM) is not in the IDLE state, this bit is set. - 0:
Master FSM is in IDLE state so the Master part of
DW_apb_i2c is not Active - 1: Master FSM is not in IDLE
state so the Master part of DW_apb_i2c is Active Note:
IC_STATUS[0]-that is, ACTIVITY bit-is the OR of
SLV_ACTIVITY and MST_ACTIVITY bits.
Reset value: 0x0
0x0 -> Master is idle
0x1 -> Master not idle
RO 0x0
4 RFF Receive FIFO Completely Full. When the receive FIFO is
completely full, this bit is set. When the receive FIFO
contains one or more empty location, this bit is cleared. - 0:
Receive FIFO is not full - 1: Receive FIFO is full Reset value:
0x0
0x0 -> Rx FIFO not full
0x1 -> Rx FIFO is full
RO 0x0
3 RFNE Receive FIFO Not Empty. This bit is set when the receive
FIFO contains one or more entries; it is cleared when the
receive FIFO is empty. - 0: Receive FIFO is empty - 1:
Receive FIFO is not empty Reset value: 0x0
0x0 -> Rx FIFO is empty
0x1 -> Rx FIFO not empty
RO 0x0
2 TFE Transmit FIFO Completely Empty. When the transmit FIFO
is completely empty, this bit is set. When it contains one or
more valid entries, this bit is cleared. This bit field does not
request an interrupt. - 0: Transmit FIFO is not empty - 1:
Transmit FIFO is empty Reset value: 0x1
0x0 -> Tx FIFO not empty
0x1 -> Tx FIFO is empty
RO 0x1
1 TFNF Transmit FIFO Not Full. Set when the transmit FIFO
contains one or more empty locations, and is cleared when
the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO
is not full Reset value: 0x1
0x0 -> Tx FIFO is full
0x1 -> Tx FIFO not full
RO 0x1
0 ACTIVITY I2C Activity Status. Reset value: 0x0
0x0 -> I2C is idle
0x1 -> I2C is active
RO 0x0
IC_TXFLR Register
Description
I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It
is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the
IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is
placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
RP2040 Datasheet
4.4. I2C 513