Datasheet

Description
I2C Enable Register
Table 505. IC_ENABLE
Register
Bits Name Description Type Reset
31:3 Reserved. - - -
2 TX_CMD_BLOCK In Master mode: - 1’b1: Blocks the transmission of data on
I2C bus even if Tx FIFO has data to transmit. - 1’b0: The
transmission of data starts on I2C bus automatically, as
soon as the first data is available in the Tx FIFO. Note: To
block the execution of Master commands, set the
TX_CMD_BLOCK bit only when Tx FIFO is empty
(IC_STATUS[2]==1) and Master is in Idle state
(IC_STATUS[5] == 0). Any further commands put in the Tx
FIFO are not executed until TX_CMD_BLOCK bit is unset.
Reset value: IC_TX_CMD_BLOCK_DEFAULT
0x0 -> Tx Command execution not blocked
0x1 -> Tx Command execution blocked
RW 0x0
1 ABORT When set, the controller initiates the transfer abort. - 0:
ABORT not initiated or ABORT done - 1: ABORT operation in
progress The software can abort the I2C transfer in master
mode by setting this bit. The software can set this bit only
when ENABLE is already set; otherwise, the controller
ignores any write to ABORT bit. The software cannot clear
the ABORT bit once set. In response to an ABORT, the
controller issues a STOP and flushes the Tx FIFO after
completing the current transfer, then sets the TX_ABORT
interrupt after the abort operation. The ABORT bit is cleared
automatically after the abort operation.
For a detailed description on how to abort I2C transfers,
refer to 'Aborting I2C Transfers'.
Reset value: 0x0
0x0 -> ABORT operation not in progress
0x1 -> ABORT operation in progress
RW 0x0
RP2040 Datasheet
4.4. I2C 511