Datasheet

Bits Name Description Type Reset
3 TX_OVER Set during transmit if the transmit buffer is filled to
IC_TX_BUFFER_DEPTH and the processor attempts to
issue another I2C command by writing to the
IC_DATA_CMD register. When the module is disabled, this
bit keeps its level until the master or slave state machines
go into idle, and when ic_en goes to 0, this interrupt is
cleared.
Reset value: 0x0
0x0 -> TX_OVER interrupt is inactive
0x1 -> TX_OVER interrupt is active
RO 0x0
2 RX_FULL Set when the receive buffer reaches or goes above the
RX_TL threshold in the IC_RX_TL register. It is
automatically cleared by hardware when buffer level goes
below the threshold. If the module is disabled
(IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset;
therefore the RX FIFO is not full. So this bit is cleared once
the IC_ENABLE bit 0 is programmed with a 0, regardless of
the activity that continues.
Reset value: 0x0
0x0 -> RX_FULL interrupt is inactive
0x1 -> RX_FULL interrupt is active
RO 0x0
1 RX_OVER Set if the receive buffer is completely filled to
IC_RX_BUFFER_DEPTH and an additional byte is received
from an external I2C device. The DW_apb_i2c
acknowledges this, but any data bytes received after the
FIFO is full are lost. If the module is disabled
(IC_ENABLE[0]=0), this bit keeps its level until the master or
slave state machines go into idle, and when ic_en goes to 0,
this interrupt is cleared.
Note: If bit 9 of the IC_CON register
(RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then
the RX_OVER interrupt never occurs, because the Rx FIFO
never overflows.
Reset value: 0x0
0x0 -> RX_OVER interrupt is inactive
0x1 -> RX_OVER interrupt is active
RO 0x0
0 RX_UNDER Set if the processor attempts to read the receive buffer
when it is empty by reading from the IC_DATA_CMD
register. If the module is disabled (IC_ENABLE[0]=0), this bit
keeps its level until the master or slave state machines go
into idle, and when ic_en goes to 0, this interrupt is cleared.
Reset value: 0x0
0x0 -> RX_UNDER interrupt is inactive
0x1 -> RX_UNDER interrupt is active
RO 0x0
IC_RX_TL Register
RP2040 Datasheet
4.4. I2C 506