Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
Bits Name Description Type Reset
6 TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is
unable to complete the intended actions on the contents of
the transmit FIFO. This situation can occur both as an I2C
master or an I2C slave, and is referred to as a 'transmit
abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE
register indicates the reason why the transmit abort takes
places.
Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO
and RX_FIFO whenever there is a transmit abort caused by
any of the events tracked by the IC_TX_ABRT_SOURCE
register. The FIFOs remains in this flushed state until the
register IC_CLR_TX_ABRT is read. Once this read is
performed, the Tx FIFO is then ready to accept more data
bytes from the APB interface.
Reset value: 0x0
0x0 -> TX_ABRT interrupt is inactive
0x1 -> TX_ABRT interrupt is active
RO 0x0
5 RD_REQ This bit is set to 1 when DW_apb_i2c is acting as a slave
and another I2C master is attempting to read data from
DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait
state (SCL=0) until this interrupt is serviced, which means
that the slave has been addressed by a remote master that
is asking for data to be transferred. The processor must
respond to this interrupt and then write the requested data
to the IC_DATA_CMD register. This bit is set to 0 just after
the processor reads the IC_CLR_RD_REQ register.
Reset value: 0x0
0x0 -> RD_REQ interrupt is inactive
0x1 -> RD_REQ interrupt is active
RO 0x0
4 TX_EMPTY The behavior of the TX_EMPTY interrupt status differs
based on the TX_EMPTY_CTRL selection in the IC_CON
register. - When TX_EMPTY_CTRL = 0: This bit is set to 1
when the transmit buffer is at or below the threshold value
set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1:
This bit is set to 1 when the transmit buffer is at or below
the threshold value set in the IC_TX_TL register and the
transmission of the address/data from the internal shift
register for the most recently popped command is
completed. It is automatically cleared by hardware when
the buffer level goes above the threshold. When
IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in
reset. There the TX FIFO looks like it has no data within it,
so this bit is set to 1, provided there is activity in the master
or slave state machines. When there is no longer any
activity, then with ic_en=0, this bit is set to 0.
Reset value: 0x0.
0x0 -> TX_EMPTY interrupt is inactive
0x1 -> TX_EMPTY interrupt is active
RO 0x0
RP2040 Datasheet
4.4. I2C 505