Datasheet

Table 488.
IC_FS_SCL_LCNT
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15:0 IC_FS_SCL_LCNT This register must be set before any I2C bus transaction
can take place to ensure proper I/O timing. This register
sets the SCL clock low period count for fast speed. It is
used in high-speed mode to send the Master Code and
START BYTE or General CALL. For more information, refer
to 'IC_CLK Frequency Configuration'.
This register goes away and becomes read-only returning
0s if IC_MAX_SPEED_MODE = standard.
This register can be written only when the I2C interface is
disabled, which corresponds to the IC_ENABLE[0] register
being set to 0. Writes at other times have no effect.
The minimum valid value is 8; hardware prevents values
less than this being written, and if attempted results in 8
being set. For designs with APB_DATA_WIDTH = 8 the
order of programming is important to ensure the correct
operation of the DW_apb_i2c. The lower byte must be
programmed first. Then the upper byte is programmed. If
the value is less than 8 then the count value gets changed
to 8.
RW 0x000d
IC_INTR_STAT Register
Description
I2C Interrupt Status Register
Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the
matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT
register.
Table 489.
IC_INTR_STAT
Register
Bits Name Description Type Reset
31:14 Reserved. - - -
13 R_MASTER_ON_H
OLD
See IC_RAW_INTR_STAT for a detailed description of
R_MASTER_ON_HOLD bit.
Reset value: 0x0
0x0 -> R_MASTER_ON_HOLD interrupt is inactive
0x1 -> R_MASTER_ON_HOLD interrupt is active
RO 0x0
12 R_RESTART_DET See IC_RAW_INTR_STAT for a detailed description of
R_RESTART_DET bit.
Reset value: 0x0
0x0 -> R_RESTART_DET interrupt is inactive
0x1 -> R_RESTART_DET interrupt is active
RO 0x0
RP2040 Datasheet
4.4. I2C 498