Datasheet

Bits Name Description Type Reset
8 CMD This bit controls whether a read or a write is performed.
This bit does not control the direction when the
DW_apb_i2con acts as a slave. It controls only the direction
when it acts as a master.
When a command is entered in the TX FIFO, this bit
distinguishes the write and read commands. In slave-
receiver mode, this bit is a 'don’t care' because writes to
this register are not required. In slave-transmitter mode, a
'0' indicates that the data in IC_DATA_CMD is to be
transmitted.
When programming this bit, you should remember the
following: attempting to perform a read operation after a
General Call command has been sent results in a TX_ABRT
interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless
bit 11 (SPECIAL) in the IC_TAR register has been cleared. If
a '1' is written to this bit after receiving a RD_REQ interrupt,
then a TX_ABRT interrupt occurs.
Reset value: 0x0
0x0 -> Master Write Command
0x1 -> Master Read Command
SC 0x0
7:0 DAT This register contains the data to be transmitted or
received on the I2C bus. If you are writing to this register
and want to perform a read, bits 7:0 (DAT) are ignored by
the DW_apb_i2c. However, when you read this register,
these bits return the value of data received on the
DW_apb_i2c interface.
Reset value: 0x0
RW 0x00
IC_SS_SCL_HCNT Register
Description
Standard Speed I2C Clock SCL High Count Register
RP2040 Datasheet
4.4. I2C 495