Datasheet

Bits Name Description Type Reset
10 RESTART This bit controls whether a RESTART is issued before the
byte is sent or received.
1 - If IC_RESTART_EN is 1, a RESTART is issued before the
data is sent/received (according to the value of CMD),
regardless of whether or not the transfer direction is
changing from the previous command; if IC_RESTART_EN
is 0, a STOP followed by a START is issued instead.
0 - If IC_RESTART_EN is 1, a RESTART is issued only if the
transfer direction is changing from the previous command;
if IC_RESTART_EN is 0, a STOP followed by a START is
issued instead.
Reset value: 0x0
0x0 -> Donot Issue RESTART before this command
0x1 -> Issue RESTART before this command
SC 0x0
9 STOP This bit controls whether a STOP is issued after the byte is
sent or received.
- 1 - STOP is issued after this byte, regardless of whether or
not the Tx FIFO is empty. If the Tx FIFO is not empty, the
master immediately tries to start a new transfer by issuing
a START and arbitrating for the bus. - 0 - STOP is not
issued after this byte, regardless of whether or not the Tx
FIFO is empty. If the Tx FIFO is not empty, the master
continues the current transfer by sending/receiving data
bytes according to the value of the CMD bit. If the Tx FIFO
is empty, the master holds the SCL line low and stalls the
bus until a new command is available in the Tx FIFO. Reset
value: 0x0
0x0 -> Donot Issue STOP after this command
0x1 -> Issue STOP after this command
SC 0x0
RP2040 Datasheet
4.4. I2C 494