Datasheet

Table 483. IC_SAR
Register
Bits Name Description Type Reset
31:10 Reserved. - - -
9:0 IC_SAR The IC_SAR holds the slave address when the I2C is
operating as a slave. For 7-bit addressing, only IC_SAR[6:0]
is used.
This register can be written only when the I2C interface is
disabled, which corresponds to the IC_ENABLE[0] register
being set to 0. Writes at other times have no effect.
Note: The default values cannot be any of the reserved
address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f.
The correct operation of the device is not guaranteed if you
program the IC_SAR or IC_TAR to a reserved value. Refer to
Table 'I2C/SMBus Definition of Bits in First Byte' for a
complete list of these reserved values.
RW 0x055
IC_DATA_CMD Register
Description
I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the
CPU reads from when retrieving bytes from RX FIFO.
The size of the register changes as follows:
Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: -
12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the
DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received;
otherwise the DW_apb_i2c will stop acknowledging.
Table 484.
IC_DATA_CMD
Register
Bits Name Description Type Reset
31:12 Reserved. - - -
11 FIRST_DATA_BYT
E
Indicates the first data byte received after the address
phase for receive transfer in Master receiver or Slave
receiver mode.
Reset value : 0x0
NOTE: In case of APB_DATA_WIDTH=8,
1. The user has to perform two APB Reads to
IC_DATA_CMD in order to get status on 11 bit.
2. In order to read the 11 bit, the user has to perform the
first data byte read [7:0] (offset 0x10) and then perform the
second read [15:8] (offset 0x11) in order to know the status
of 11 bit (whether the data received in previous read is a
first data byte or not).
3. The 11th bit is an optional read field, user can ignore 2nd
byte read [15:8] (offset 0x11) if not interested in
FIRST_DATA_BYTE status.
0x0 -> Sequential data byte received
0x1 -> Non sequential data byte received
RO 0x0
RP2040 Datasheet
4.4. I2C 493