Datasheet

Bits Name Description Type Reset
2:1 SPEED These bits control at which speed the DW_apb_i2c
operates; its setting is relevant only if one is operating the
DW_apb_i2c in master mode. Hardware protects against
illegal values being programmed by software. These bits
must be programmed appropriately for slave mode also, as
it is used to capture correct value of spike filter as per the
speed mode.
This register should be programmed only with a value in
the range of 1 to IC_MAX_SPEED_MODE; otherwise,
hardware updates this register with the value of
IC_MAX_SPEED_MODE.
1: standard mode (100 kbit/s)
2: fast mode (<=400 kbit/s) or fast mode plus
(<=1000Kbit/s)
3: high speed mode (3.4 Mbit/s)
Note: This field is not applicable when
IC_ULTRA_FAST_MODE=1
0x1 -> Standard Speed mode of operation
0x2 -> Fast or Fast Plus mode of operation
0x3 -> High Speed mode of operation
RW 0x2
0 MASTER_MODE This bit controls whether the DW_apb_i2c master is
enabled.
NOTE: Software should ensure that if this bit is written with
'1' then bit 6 should also be written with a '1'.
0x0 -> Master mode is disabled
0x1 -> Master mode is enabled
RW 0x1
IC_TAR Register
Description
I2C Target Address Register
This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to
0.
Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands
in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is
not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.
Table 482. IC_TAR
Register
Bits Name Description Type Reset
31:12 Reserved. - - -
RP2040 Datasheet
4.4. I2C 491