Datasheet

Ê MIN_SCL_LOWtime = Minimum Low Period
Ê MIN_SCL_LOWtime = 4700 ns for 100 kbps,
Ê 1300 ns for 400 kbps,
Ê 500 ns for 1000 kbps,
Ê 160 ns for 3.4Mbs, bus loading = 100pF
Ê 320 ns for 3.4Mbs, bus loading = 400pF
Ê OSCFREQ = ic_clk Clock Frequency (Hz).
For example:
Ê OSCFREQ = 100 MHz
Ê I2Cmode = fast, 400 kbit/s
Ê MIN_SCL_HIGHtime = 600 ns.
Ê MIN_SCL_LOWtime = 1300 ns.
Ê IC_xCNT = (ROUNDUP(MIN_SCL_HIGH_LOWtime*OSCFREQ,0))
Ê IC_HCNT = (ROUNDUP(600 ns * 100 MHz,0))
Ê IC_HCNTSCL PERIOD = 60
Ê IC_LCNT = (ROUNDUP(1300 ns * 100 MHz,0))
Ê IC_LCNTSCL PERIOD = 130
Ê Actual MIN_SCL_HIGHtime = 60*(1/100 MHz) = 600 ns
Ê Actual MIN_SCL_LOWtime = 130*(1/100 MHz) = 1300 ns
4.4.15. DMA Controller Interface
The DW_apb_i2c has built-in DMA capability; it has a handshaking interface to the DMA Controller to request and control
transfers. The APB bus is used to perform the data transfer to or from the DMA. DMA transfers are transferred as single
accesses as data rate is relatively low.
4.4.15.1. Enabling the DMA Controller Interface
To enable the DMA Controller interface on the DW_apb_i2c, you must write the DMA Control Register (IC_DMA_CR).
Writing a one into the TDMAE bit field of IC_DMA_CR register enables the DW_apb_i2c transmit handshaking interface.
Writing a one into the RDMAE bit field of the IC_DMA_CR register enables the DW_apb_i2c receive handshaking interface.
4.4.15.2. Overview of Operation
TO DO: GRAHAM/LIAM: Review this section
The DMA Controller is programmed with the number of data items (block size) that are to be transmitted or received by
DW_apb_i2c.
The block is broken into a number of transactions, each initiated by a request from the DW_apb_i2c. Each transfer is one
item on the bus.
For example, where the block size programmed into the DMA Controller is four. The DMA block transfer consists of a
series of four single transactions. If the DW_apb_i2c makes a transmit request to this channel, a single data item is written
to the DW_apb_i2c TX FIFO. Similarly, if the DW_apb_i2c makes a receive request to this channel, a single data item is
read from the DW_apb_i2c RX FIFO. Four separate requests must be made to this DMA channel before all four data items
are written or read.
RP2040 Datasheet
4.4. I2C 486