Datasheet

Timing Parameter Symbol Standard Speed Fast Speed / Fast Speed Plus
Bus free time between a
STOP and a START
condition
tBUF IC_SS_SCL_LCNT IC_FS_SCL_LCNT
Spike length tSP IC_FS_SPKLEN IC_FS_SPKLEN
Data hold time tHD;DAT IC_SDA_HOLD IC_SDA_HOLD
Data setup time tSU;DAT IC_SDA_SETUP IC_SDA_SETUP
4.4.14.1. Minimum High and Low Counts in SS, FS, and FM+ Modes.
When the DW_apb_i2c operates as an I2C master, in both transmit and receive transfers:
•
IC_SS_SCL_LCNT and IC_FS_SCL_LCNT register values must be larger than IC_FS_SPKLEN + 7.
•
IC_SS_SCL_HCNT and IC_FS_SCL_HCNT register values must be larger than IC_FS_SPKLEN + 5.
Details regarding the DW_apb_i2c high and low counts are as follows:
•
The minimum value of IC_*_SPKLEN + 7 for the *_LCNT registers is due to the time required for the DW_apb_i2c to
drive SDA after a negative edge of SCL.
•
The minimum value of IC_*_SPKLEN + 5 for the *_HCNT registers is due to the time required for the DW_apb_i2c to
sample SDA during the high period of SCL.
•
The DW_apb_i2c adds one cycle to the programmed *_LCNT value in order to generate the low period of the SCL
clock; this is due to the counting logic for SCL low counting to (*_LCNT + 1).
•
The DW_apb_i2c adds IC_*_SPKLEN + 7 cycles to the programmed *_HCNT value in order to generate the high
period of the SCL clock; this is due to the following factors:
◦
The counting logic for SCL high counts to (*_HCNT+1).
◦
The digital filtering applied to the SCL line incurs a delay of SPKLEN + 2 ic_clk cycles, where SPKLEN is:
▪
IC_FS_SPKLEN if the component is operating in SS or FS
◦
Whenever SCL is driven one to zero by the DW_apb_i2c—that is, completing the SCL high time—an internal logic
latency of three ic_clk cycles is incurred. Consequently, the minimum SCL low time of which the DW_apb_i2c is
capable is nine ic_clk periods (7 + 1 + 1), while the minimum SCL high time is thirteen ic_clk periods (6 + 1 + 3 +
3).

NOTE
The total high time and low time of SCL generated by the DW_apb_i2c master is also influenced by the rise time and fall
time of the SCL line, as shown in the illustration and equations in Figure 84. It should be noted that the SCL rise and fall
time parameters vary, depending on external factors such as:
•
Characteristics of IO driver
•
Pull-up resistor value
•
Total capacitance on SCL line, and so on
These characteristics are beyond the control of the DW_apb_i2c.
RP2040 Datasheet
4.4. I2C 483