Datasheet


NOTE
•
Because the minimum value that can be programmed into the IC_FS_SPKLEN register is one, the spike length
specification can be exceeded for low frequencies of ic_clk. Consider the simple example of a 10 MHz (100 ns
period) ic_clk; in this case, the minimum spike length that can be programmed is 100 ns, which means that
spikes up to this length are suppressed.
•
Standard synchronization logic (two flip-flops in series) is implemented upstream of the spike suppression logic
and is not affected in any way by the contents of the spike length registers or the operation of the spike
suppression logic; the two operations (synchronization and spike suppression) are completely independent.
Because the SCL and SDA inputs are asynchronous to ic_clk, there is one ic_clk cycle uncertainty in the sampling
of these signals; that is, depending on when they occur relative to the rising edge of ic_clk, spikes of the same
original length might show a difference of one ic_clk cycle after being sampled.
•
Spike suppression is symmetrical; that is, the behaviour is exactly the same for transitions from zero to one and
from one to zero.
4.4.12. Fast Mode Plus Operation
In fast mode plus, the DW_apb_i2c allows the fast mode operation to be extended to support speeds up to 1000 Kb/s. To
enable the DW_apb_i2c for fast mode plus operation, perform the following steps before initiating any data transfer:
1.
Set ic_clk frequency greater than or equal to 32 MHz (refer to Section 4.4.14.2.1).
2. Program the IC_CON register [2:1] = 2’b10 for fast mode or fast mode plus.
3.
Program IC_FS_SCL_LCNT and IC_FS_SCL_HCNT registers to meet the fast mode plus SCL (refer to Section 4.4.14).
4. Program the IC_FS_SPKLEN register to suppress the maximum spike of 50ns.
5. Program the IC_SDA_SETUP register to meet the minimum data setup time (tSU; DAT).
4.4.13. Bus Clear Feature
DW_apb_i2c supports the bus clear feature that provides graceful recovery of data SDA and clock SCL lines during unlikely
events in which either the clock or data line is stuck at LOW.
4.4.13.1. SDA Line Stuck at LOW Recovery
In case of SDA line stuck at LOW, the master performs the following actions to recover as shown in Figure 82 and Figure
83:
1. Master sends a maximum of nine clock pulses to recover the bus LOW within those nine clocks.
◦
The number of clock pulses will vary with the number of bits that remain to be sent by the slave. As the
maximum number of bits is nine, master sends up to nine clock pluses and allows the slave to recover it.
◦
The master attempts to assert a Logic 1 on the SDA line and check whether SDA is recovered. If the SDA is not
recovered, it will continue to send a maximum of nine SCL clocks.
2.
If SDA line is recovered within nine clock pulses then the master will send the STOP to release the bus.
3.
If SDA line is not recovered even after the ninth clock pulse then system needs a hardware reset.
RP2040 Datasheet
4.4. I2C 481