Datasheet

they remain stable for a predetermined amount of ic_clk cycles before they are sampled internally. There is one separate
counter for each signal (SCL and SDA). The number of ic_clk cycles can be programmed by the user and should be
calculated taking into account the frequency of ic_clk and the relevant spike length specification. Each counter is started
whenever its input signal changes its value. Depending on the behaviour of the input signal, one of the following scenarios
occurs:
•
The input signal remains unchanged until the counter reaches its count limit value. When this happens, the internal
version of the signal is updated with the input value, and the counter is reset and stopped. The counter is not
restarted until a new change on the input signal is detected.
•
The input signal changes again before the counter reaches its count limit value. When this happens, the counter is
reset and stopped, but the internal version of the signal is not updated. The counter remains stopped until a new
change on the input signal is detected.
The timing diagram in Figure 81 illustrates the behaviour described above.
Recovery Clocks
Spike length counter
SCL
Internal filtered SCL
0 1 2 3 0 1 2 3 4 5 0
Figure 81. Spike
Suppression Example

NOTE
There is a 2-stage synchronizer on the SCL input, but for the sake of simplicity this synchronization delay was not
included in the timing diagram in Figure 81.
The I2C Bus Specification calls for different maximum spike lengths according to the operating mode—50 ns for SS and
FS, so this register is required to store the values needed:
•
Register IC_FS_SPKLEN holds the maximum spike length for SS and FS modes
This register is 8 bits wide and accessible through the APB interface for read and write purposes; however, they can be
written to only when the DW_apb_i2c is disabled. The minimum value that can be programmed into these registers is one;
attempting to program a value smaller than one results in the value one being written.
The default value for these registers is based on the value of 100ns for ic_clk period, so does should be updated for the
clk_sys period in use on RP2040.
RP2040 Datasheet
4.4. I2C 480