Datasheet

Offset Name Info
0x06c DIV_SDIVISOR Divider signed divisor
0x070 DIV_QUOTIENT Divider result quotient
0x074 DIV_REMAINDER Divider result remainder
0x078 DIV_CSR Control and status register for divider.
0x080 INTERP0_ACCUM0 Read/write access to accumulator 0
0x084 INTERP0_ACCUM1 Read/write access to accumulator 1
0x088 INTERP0_BASE0 Read/write access to BASE0 register.
0x08c INTERP0_BASE1 Read/write access to BASE1 register.
0x090 INTERP0_BASE2 Read/write access to BASE2 register.
0x094 INTERP0_POP_LANE0 Read LANE0 result, and simultaneously write lane results to both
accumulators (POP).
0x098 INTERP0_POP_LANE1 Read LANE1 result, and simultaneously write lane results to both
accumulators (POP).
0x09c INTERP0_POP_FULL Read FULL result, and simultaneously write lane results to both
accumulators (POP).
0x0a0 INTERP0_PEEK_LANE0 Read LANE0 result, without altering any internal state (PEEK).
0x0a4 INTERP0_PEEK_LANE1 Read LANE1 result, without altering any internal state (PEEK).
0x0a8 INTERP0_PEEK_FULL Read FULL result, without altering any internal state (PEEK).
0x0ac INTERP0_CTRL_LANE0 Control register for lane 0
0x0b0 INTERP0_CTRL_LANE1 Control register for lane 1
0x0b4 INTERP0_ACCUM0_ADD Values written here are atomically added to ACCUM0
0x0b8 INTERP0_ACCUM1_ADD Values written here are atomically added to ACCUM1
0x0bc INTERP0_BASE_1AND0 On write, the lower 16 bits go to BASE0, upper bits to BASE1
simultaneously.
0x0c0 INTERP1_ACCUM0 Read/write access to accumulator 0
0x0c4 INTERP1_ACCUM1 Read/write access to accumulator 1
0x0c8 INTERP1_BASE0 Read/write access to BASE0 register.
0x0cc INTERP1_BASE1 Read/write access to BASE1 register.
0x0d0 INTERP1_BASE2 Read/write access to BASE2 register.
0x0d4 INTERP1_POP_LANE0 Read LANE0 result, and simultaneously write lane results to both
accumulators (POP).
0x0d8 INTERP1_POP_LANE1 Read LANE1 result, and simultaneously write lane results to both
accumulators (POP).
0x0dc INTERP1_POP_FULL Read FULL result, and simultaneously write lane results to both
accumulators (POP).
0x0e0 INTERP1_PEEK_LANE0 Read LANE0 result, without altering any internal state (PEEK).
0x0e4 INTERP1_PEEK_LANE1 Read LANE1 result, without altering any internal state (PEEK).
0x0e8 INTERP1_PEEK_FULL Read FULL result, without altering any internal state (PEEK).
RP2040 Datasheet
2.3. Processor subsystem 47