Datasheet

4.4.10.2.1. Initial Configuration
To use the DW_apb_i2c as a master perform the following steps:
1. Disable the DW_apb_i2c by writing zero to IC_ENABLE.ENABLE.
2. Write to the IC_CON register to set the maximum speed mode supported (bits 2:1) and the desired speed of the
DW_apb_i2c master-initiated transfers, either 7-bit or 10-bit addressing (bit 4). Ensure that bit six
(IC_SLAVE_DISABLE) is written with a ‘1’ and bit zero (MASTER_MODE) is written with a ‘1’.
Note: Slaves and masters do not have to be programmed with the same type of 7-bit or 10-bit address. For instance, a
slave can be programmed with 7-bit addressing and a master with 10-bit addressing, and vice versa.
1. Write to the IC_TAR register the address of the I2C device to be addressed (bits 9:0). This register also indicates
whether a General Call or a START BYTE command is going to be performed by I2C.
2. Enable the DW_apb_i2c by writing a one to IC_ENABLE.ENABLE.
3. Now write transfer direction and data to be sent to the IC_DATA_CMD register. If the IC_DATA_CMD register is
written before the DW_apb_i2c is enabled, the data and commands are lost as the buffers are kept cleared when
DW_apb_i2c is disabled. This step generates the START condition and the address byte on the DW_apb_i2c. Once
DW_apb_i2c is enabled and there is data in the TX FIFO, DW_apb_i2c starts reading the data.
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NOTE
Depending on the reset values chosen, steps two, three, four, and five may not be necessary because the reset values
can be configured. The values stored are static and do not need to be reprogrammed if the DW_apb_i2c is disabled,
with the exception of the transfer direction and data.
4.4.10.2.2. Master Transmit and Master Receive
The DW_apb_i2c supports switching back and forth between reading and writing dynamically. To transmit data, write the
data to be written to the lower byte of the I2C Rx/Tx Data Buffer and Command Register (IC_DATA_CMD). The CMD bit [8]
should be written to zero for I2C write operations. Subsequently, a read command may be issued by writing “don’t cares”
to the lower byte of the IC_DATA_CMD register, and a one should be written to the CMD bit. The DW_apb_i2c master
continues to initiate transfers as long as there are commands present in the transmit FIFO. If the transmit FIFO becomes
empty the master either inserts a STOP condition after completing the current transfers.
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If set to one, it issues a STOP condition after completing the current transfer.
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If set to zero, it holds SCL low until next command is written to the transmit FIFO.
For more details, refer to Section 4.4.7.
4.4.10.3. Disabling DW_apb_i2c
The register IC_ENABLE_STATUS is added to allow software to unambiguously determine when the hardware has
completely shutdown in response to IC_ENABLE.ENABLE being set from one to zero.
Only one register is required to be monitored, as opposed to monitoring two registers (IC_STATUS and
IC_RAW_INTR_STAT) which was a requirement for earlier versions of DW_apb_i2c.
RP2040 Datasheet
4.4. I2C 478