Datasheet


NOTE
If the Rx FIFO is completely filled with data when a byte is pushed, then the DW_apb_i2c slave holds the I2C SCL line
low until the Rx FIFO has some space, and then continues with the next read request.
1. DW_apb_i2c asserts the RX_FULL interrupt IC_RAW_INTR_STAT.RX_FULL. If the RX_FULL interrupt has been
masked, due to setting IC_INTR_MASK.M_RX_FULL register to zero or setting IC_TX_TL to a value larger than zero,
then it is recommended that a timing routine (described in Section 4.4.10.1.2) be implemented for periodic reads of
the IC_STATUS register. Reads of the IC_STATUS register, with bit 3 (RFNE) set at one, must then be treated by
software as the equivalent of the RX_FULL interrupt being asserted.
2. Software may read the byte from the IC_DATA_CMD register (bits 7:0).
3. The other master device may hold the I2C bus by issuing a RESTART condition, or release the bus by issuing a STOP
condition.
4.4.10.1.4. Slave-Transfer Operation For Bulk Transfers
In the standard I2C protocol, all transactions are single byte transactions and the programmer responds to a remote
master read request by writing one byte into the slave’s TX FIFO. When a slave (slave-transmitter) is issued with a read
request (RD_REQ) from the remote master (master-receiver), at a minimum there should be at least one entry placed into
the slave-transmitter’s TX FIFO. DW_apb_i2c is designed to handle more data in the TX FIFO so that subsequent read
requests can take that data without raising an interrupt to get more data. Ultimately, this eliminates the possibility of
significant latencies being incurred between raising the interrupt for data each time had there been a restriction of having
only one entry placed in the TX FIFO. This mode only occurs when DW_apb_i2c is acting as a slave-transmitter. If the
remote master acknowledges the data sent by the slave-transmitter and there is no data in the slave’s TX FIFO, the
DW_apb_i2c holds the I2C SCL line low while it raises the read request interrupt (RD_REQ) and waits for data to be written
into the TX FIFO before it can be sent to the remote master.
If the RD_REQ interrupt is masked, due to IC_INTR_STAT.M_RD_REQ set to zero, then it is recommended that a timing
routine be used to activate periodic reads of the IC_RAW_INTR_STAT register. Reads of IC_RAW_INTR_STAT that return
bit five (R_RD_REQ) set to one must be treated as the equivalent of the RD_REQ interrupt referred to in this section. This
timing routine is similar to that described in Section 4.4.10.1.2.
The RD_REQ interrupt is raised upon a read request, and like interrupts, must be cleared when exiting the interrupt service
handling routine (ISR). The ISR allows you to either write one byte or more than one byte into the Tx FIFO. During the
transmission of these bytes to the master, if the master acknowledges the last byte, then the slave must raise the
RD_REQ again because the master is requesting for more data. If the programmer knows in advance that the remote
master is requesting a packet of 'n' bytes, then when another master addresses DW_apb_i2c and requests data, the Tx
FIFO could be written with 'n' bytes and the remote master receives it as a continuous stream of data. For example, the
DW_apb_i2c slave continues to send data to the remote master as long as the remote master is acknowledging the data
sent and there is data available in the Tx FIFO. There is no need to hold the SCL line low or to issue RD_REQ again.
If the remote master is to receive 'n' bytes from the DW_apb_i2c but the programmer wrote a number of bytes larger than
'n' to the Tx FIFO, then when the slave finishes sending the requested 'n' bytes, it clears the Tx FIFO and ignores any
excess bytes.
The DW_apb_i2c generates a transmit abort (TX_ABRT) event to indicate the clearing of the Tx FIFO in this example. At
the time an ACK/NACK is expected, if a NACK is received, then the remote master has all the data it wants. At this time, a
flag is raised within the slave’s state machine to clear the leftover data in the Tx FIFO. This flag is transferred to the
processor bus clock domain where the FIFO exists and the contents of the Tx FIFO is cleared at that time.
4.4.10.2. Master Mode Operation
This section discusses master mode procedures.
RP2040 Datasheet
4.4. I2C 477