Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
NOTE
The value of 10 is recommended here because this is approximately the amount of time required for a single byte of
data transferred on the I2C bus.
1. If there is any data remaining in the Tx FIFO before receiving the read request, then the DW_apb_i2c asserts a
TX_ABRT interrupt (bit six of the IC_RAW_INTR_STAT register) to flush the old data from the TX FIFO. If the TX_ABRT
interrupt has been masked, due to IC_INTR_MASK.M_TX_ABRT being set to zero, then it is recommended that re-
using the timing routine (described in the previous step), or a similar one, be used to read the IC_RAW_INTR_STAT
register.
NOTE
Because the DW_apb_i2c’s Tx FIFO is forced into a flushed/reset state whenever a TX_ABRT event occurs, it is
necessary for software to release the DW_apb_i2c from this state by reading the IC_CLR_TX_ABRT register before
attempting to write into the Tx FIFO. See register IC_RAW_INTR_STAT for more details.
a. Reads that indicate bit six (R_TX_ABRT) being set to one must be treated as the equivalent of the TX_ABRT interrupt
being asserted.
b. There is no further action required from software.
c. The timing interval used should be similar to that described in the previous step for the IC_RAW_INTR_STATRD_REQ
register.
1. Software writes to the IC_DATA_CMD register with the data to be written (by writing a ‘0’ in bit 8).
2. Software must clear the RD_REQ and TX_ABRT interrupts (bits five and six, respectively) of the
IC_RAW_INTR_STAT register before proceeding. If the RD_REQ and/or TX_ABRT interrupts have been masked,
then clearing of the IC_RAW_INTR_STAT register will have already been performed when either the R_RD_REQ
or R_TX_ABRT bit has been read as one.
3.
The DW_apb_i2c releases the SCL and transmits the byte.
4. The master may hold the I2C bus by issuing a RESTART condition or release the bus by issuing a STOP
condition.
NOTE
Slave-Transmitter Operation for a Single Byte is not applicable in Ultra-Fast Mode as Read transfers are not supported.
4.4.10.1.3. Slave-Receiver Operation for a Single Byte
When another I2C master device on the bus addresses the DW_apb_i2c and is sending data, the DW_apb_i2c acts as a
slave-receiver and the following steps occur:
1. The other I2C master device initiates an I2C transfer with an address that matches the DW_apb_i2c’s slave address
in the IC_SAR register.
2. The DW_apb_i2c acknowledges the sent address and recognizes the direction of the transfer to indicate that the
DW_apb_i2c is acting as a slave-receiver.
3. DW_apb_i2c receives the transmitted byte and places it in the receive buffer.
RP2040 Datasheet
4.4. I2C 476