Datasheet

Table Of Contents
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with command
(read operation in this example)
Last command popped
from Tx FIFO with
STOP bit not set
Tx FIFO loaded
with new command
Next command loaded into
Tx FIFO has RESTART bit set
Master issues NOT ACK as
required before RESTART
when operating as receiver
Master issues RESTART and
initiates new transmission
Because STOP bit
was not set on last
command popped
from Tx FIFO, Master
holds SCL low
Command availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
RR Ack Ack Nak Ack
S
R
Figure 78. Master
Receiver — First
Command Loaded
After Tx FIFO Allowed
to Empty/Restart Bit
Set
4.4.8. Multiple Master Arbitration
The DW_apb_i2c bus protocol allows multiple masters to reside on the same bus. If there are two masters on the same
I2C-bus, there is an arbitration procedure if both try to take control of the bus at the same time by generating a START
condition at the same time. Once a master (for example, a microcontroller) has control of the bus, no other master can
take control until the first master sends a STOP condition and places the bus in an idle state.
Arbitration takes place on the SDA line, while the SCL line is one. The master, which transmits a one while the other master
transmits zero, loses arbitration and turns off its data output stage. The master that lost arbitration can continue to
generate clocks until the end of the byte transfer. If both masters are addressing the same slave device, the arbitration
could go into the data phase.
Upon detecting that it has lost arbitration to another master, the DW_apb_i2c will stop generating SCL (will disable the
output driver). Figure 79 illustrates the timing of when two masters are arbitrating on the bus.
CLKA
DATA2
SDA
SCL
MSB
MSB
MSB
‘0’
matching data
DATA1 loses arbitration
SDA mirrors DATA2
SDA lines up
with DATA1
START condition
‘1’
Figure 79. Multiple
Master Arbitration
Control of the bus is determined by address or master code and data sent by competing masters, so there is no central
master nor any order of priority on the bus.
Arbitration is not allowed between the following conditions:
A RESTART condition and a data bit
A STOP condition and a data bit
A RESTART condition and a STOP condition
NOTE
Slaves are not involved in the arbitration process.
4.4.9. Clock Synchronization
When two or more masters try to transfer information on the bus at the same time, they must arbitrate and synchronize
the SCL clock. All masters generate their own clock to transfer messages. Data is valid only during the high period of SCL
RP2040 Datasheet
4.4. I2C 473