Datasheet

SDA
SCL
FIFO_
EMPTY
A
6
S
Next byte in Tx FIFO
has RESTART bit set
Because next byte on Tx FIFO has
been tagged with RESTART bit,
Master issues RESTART and
initiates new transmission
Data availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
6
D
7
W Ack Ack AckWAck
S
R
Tx FIFO loaded with data
(write data in this example)
Figure 73. Master
Transmitter — Restart
Bit of IC_DATA_CMD
Is Set
Figure 74 illustrates the same situation, but during operation as a master receiver.
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with command
(read operation in this example)
Next command in Tx FIFO
has RESTART bit set
Master issues NOT ACK as
required before RESTART
when operating as receiver
Because next command on Tx FIFO
has been tagged with RESTART bit,
Master issues RESTART and
initiates new transmission
Command availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
RR Ack Ack Nak Ack
S
R
Figure 74. Master
Receiver — Restart Bit
of IC_DATA_CMD Is
Set
Figure 75 illustrates operation as a master transmitter where the Stop bit of the IC_DATA_CMD register is set and the Tx
FIFO is not empty
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with data
(write data in this example)
One byte (not last one)
is popped from Tx FIFO
with STOP bit set
Because more data is available in
Tx FIFO, a new transmission is
immediately initiated (provided
master is granted access to bus)
Data availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
6
D
7
W Ack Ack AckWAck
SP
Because STOP bit was set on last
byte popped from Tx FIFO, Master
generates STOP condition
Figure 75. Master
Transmitter — Stop Bit
of IC_DATA_CMD
Set/Tx FIFO Not Empty
Figure 76 illustrates operation as a master transmitter where the first byte loaded into the Tx FIFO is allowed to go empty
with the Restart bit set
SDA
SCL
FIFO_
EMPTY
A
6
S
Last byte popped
from Tx FIFO with
STOP bit not set
Tx FIFO loaded
with new command
Master issues RESTART and
initiates new transmission
Because STOP bit was
not set on last byte
popped from Tx FIFO,
Master holds SCL low
Data availability triggers START
condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
6
D
7
W Ack Ack AckWAck
S
R
Tx FIFO loaded with data
(write data in this example)
Figure 76. Master
Transmitter — First
Byte Loaded Into Tx
FIFO Allowed to
Empty, Restart Bit Set
Figure 77 illustrates operation as a master receiver where the Stop bit of the IC_DATA_CMD register is set and the Tx FIFO
is not empty
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with command
(read operation in this example)
One command
(not last one) is
popped from
Tx FIFO with
STOP bit set
Because more commands
are available inTx FIFO, a
new transmission is
immediately initiated
(provided master is granted
access to bus)
Because STOP bit was
set on last command
popped from Tx FIFO,
Master generates
STOP condition
Command availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
RR Ack Ack Ack
SP
Nak
Figure 77. Master
Receiver — Stop Bit of
IC_DATA_CMD Set/Tx
FIFO Not Empty
Figure 78 illustrates operation as a master receiver where the first command loaded after the Tx FIFO is allowed to empty
and the Restart bit is set
RP2040 Datasheet
4.4. I2C 472