Datasheet

5. Master generates a RESTART (R) condition.
A hardware receiver does not respond to the START BYTE because it is a reserved address and resets after the RESTART
condition is generated.
4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
When operating as a master, the DW_apb_i2c component supports the mode of Tx FIFO management illustrated in Figure
70
4.4.7.1. Tx FIFO Management
The component does not generate a STOP if the Tx FIFO becomes empty; in this situation the component holds the SCL
line low, stalling the bus until a new entry is available in the Tx FIFO. A STOP condition is generated only when the user
specifically requests it by setting bit nine (Stop bit) of the command written to IC_DATA_CMD register. Figure 70 shows
the bits in the IC_DATA_CMD register.
IC_DATA_CMD
Restart
Data Read/Write field; data retrieved from slave is read from
this field; data to be sent to slave is written to this field
CDM Write-only field; this bit determines whether transfer to
be carried out is Read (CMD=1) or Write (CMD=0)
Stop Write-only field; this bit determines whether STOP is
generated after data byte is sent or received
Restart Write-only field; this bit determines whether RESTART
(or STOP followed by START in case or restart
capability is not enabled) is generated before data is
sent or received
9 8 7 0
Stop CMD DATA
Figure 70.
IC_DATA_CMD
Register
Figure 71 illustrates the behaviour of the DW_apb_i2c when the Tx FIFO becomes empty while operating as a master
transmitter, as well as showing the generation of a STOP condition.
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with data
(write data in this example)
Last byte popped from
Tx FIFO, with STOP bit
not set
Master releases SCL line and
resumes transmission because
new data became available
Data availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
D
6
D
7
D
5
D
4
D
3
D
2
D
1
D
0
W Ack Ack AckAck
P
Because STOP bit was not set on
last byte popped from Tx FIFO,
Master holds SCL low
Tx FIFO loaded
with new data
Last byte popped from Tx FIFO
with STOP bit set
STOP bit enabled triggers
STOP condition on bus
Figure 71. Master
Transmitter - Tx FIFO
Empties/STOP
Generation
Figure 72 illustrates the behaviour of the DW_apb_i2c when the Tx FIFO becomes empty while operating as a master
receiver, as well as showing the generation of a STOP condition.
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with command
(read operation in this example)
Last command
popped from Tx
FIFO, with STOP bit
not set
Tx FIFO loaded
with new command
Last command popped from
Tx FIFO with STOP bit set
STOP bit enabled triggers
STOP condition on bus
Master releases SCL line and
resumes transmission
because new command
became available
Because STOP bit was
not set on last
command popped
from Tx FIFO, Master
holds SCL low
Command availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
R Ack Ack NakAck
S
Figure 72. Master
Receiver - Tx FIFO
Empties/STOP
Generation
Figure 73 and Figure 74 illustrate configurations where the user can control the generation of RESTART conditions on the
I2C bus. If bit 10 (Restart) of the IC_DATA_CMD register is set and the restart capability is enabled (IC_RESTART_EN=1), a
RESTART is generated before the data byte is written to or read from the slave. If the restart capability is not enabled a
STOP followed by a START is generated in place of the RESTART. Figure 73 illustrates this situation during operation as a
master transmitter.
RP2040 Datasheet
4.4. I2C 471