Datasheet

4.4.6.3.2. Master-Receiver and Slave-Transmitter
If the master is receiving data as shown in Figure 68, then the master responds to the slave-transmitter with an
acknowledge pulse after a byte of data has been received, except for the last byte. This is the way the master-receiver
notifies the slave-transmitter that this is the last byte. The slave-transmitter relinquishes the SDA line after detecting the No
Acknowledge (NACK) so that the master can issue a STOP condition.
S
For 7-bit Address
R/W
‘1’ (read)
A ADATA A PDATASlave Address
‘1’ (read)
S
For 10-bit Address
From Master to Slave A = Acknowledge (SDA low)
A = No Acknowledge (SDA high)
S = START Condition
R = RESTART Condition
P = STOP Condition
From Slave to Master
R/W
‘0’ (write)
A A ASr A PDATA
Slave Address
First 7 bits
Slave Address
Second Byte
R/W
Slave Address
First 7 bits
‘11110xxx’ ‘11110xxx’
Figure 68. I2C Master-
Receiver Protocol
When a master does not want to relinquish the bus with a STOP condition, the master can issue a RESTART condition.
This is identical to a START condition except it occurs after the ACK pulse. Operating in master mode, the DW_apb_i2c
can then communicate with the same slave using a transfer of a different direction. For a description of the combined
format transactions that the DW_apb_i2c supports, refer to Section 4.4.5.2.

NOTE
The DW_apb_i2c must be completely disabled before the target slave address register (IC_TAR) can be
reprogrammed.
4.4.6.4. START BYTE Transfer Protocol
The START BYTE transfer protocol is set up for systems that do not have an on-board dedicated I2C hardware module.
When the DW_apb_i2c is addressed as a slave, it always samples the I2C bus at the highest speed supported so that it
never requires a START BYTE transfer. However, when DW_apb_i2c is a master, it supports the generation of START
BYTE transfers at the beginning of every transfer in case a slave device requires it.
This protocol consists of seven zeros being transmitted followed by a one, as illustrated in Figure 69. This allows the
processor that is polling the bus to under-sample the address phase until zero is detected. Once the microcontroller
detects a zero, it switches from the under sampling rate to the correct rate of the master.
SDA
SCL
1 2
S
Ack
(HIGH)
dummy
acknowledge
Sr
7 8 9
start byte 00000001
Figure 69. I2C Start
Byte Transfer
The START BYTE procedure is as follows:
1. Master generates a START condition.
2. Master transmits the START byte (0000 0001).
3. Master transmits the ACK clock pulse. (Present only to conform with the byte handling format used on the bus)
4. No slave sets the ACK signal to zero.
RP2040 Datasheet
4.4. I2C 470