Datasheet

Each slave has a unique address that is determined by the system designer. When a master wants to communicate with
a slave, the master transmits a START/RESTART condition that is then followed by the slave’s address and a control bit
(R/W) to determine if the master wants to transmit data or receive data from the slave. The slave then sends an
acknowledge (ACK) pulse after the address.
If the master (master-transmitter) is writing to the slave (slave-receiver), the receiver gets one byte of data. This
transaction continues until the master terminates the transmission with a STOP condition. If the master is reading from a
slave (master-receiver), the slave transmits (slave-transmitter) a byte of data to the master, and the master then
acknowledges the transaction with the ACK pulse. This transaction continues until the master terminates the
transmission by not acknowledging (NACK) the transaction after the last byte is received, and then the master issues a
STOP condition or addresses another slave after issuing a RESTART condition. This behaviour is illustrated in Figure 63.
SDA
SCL
S
or
R
START or RESTART Condition
P
or
R
R
or
P
STOP AND RESTART ConditionByte Complete Interrupt
within Slave
SCL held low while
servicing interrupts
MSB
1 2 1 2 93-87 8 9
LSB ACK
from slave from receiver
ACK
Figure 63. Data
transfer on the I2C
Bus
The DW_apb_i2c is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the SCL line
is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain or open-collector to perform
wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the maximum capacitance
specification of 400 pF. Data is transmitted in byte packages.
The I2C protocols implemented in DW_apb_i2c are described in more details in Section 4.4.6 section.
4.4.5.1. START and STOP Generation
When operating as an I2C master, putting data into the transmit FIFO causes the DW_apb_i2c to generate a START
condition on the I2C bus. Writing a 1 to IC_DATA_CMD.STOP causes the DW_apb_i2c to generate a STOP condition on the
I2C bus; a STOP condition is not issued if this bit is not set, even if the transmit FIFO is empty.
When operating as a slave, the DW_apb_i2c does not generate START and STOP conditions, as per the protocol. However,
if a read request is made to the DW_apb_i2c, it holds the SCL line low until read data has been supplied to it. This stalls the
I2C bus until read data is provided to the slave DW_apb_i2c, or the DW_apb_i2c slave is disabled by writing a 0 to
IC_ENABLE.ENABLE.
4.4.5.2. Combined Formats
The DW_apb_i2c supports mixed read and write combined format transactions in both 7-bit and 10-bit addressing modes.
The DW_apb_i2c does not support mixed address and mixed address format—that is, a 7-bit address transaction followed
by a 10-bit address transaction or vice versa—combined format transactions. To initiate combined format transfers,
IC_CON.IC_RESTART_EN should be set to 1. With this value set and operating as a master, when the DW_apb_i2c
completes an I2C transfer, it checks the transmit FIFO and executes the next transfer. If the direction of this transfer
differs from the previous transfer, the combined format is used to issue the transfer. If the transmit FIFO is empty when
the current I2C transfer completes:
•
IC_DATA_CMD.STOP is checked and:
◦
If set to 1, a STOP bit is issued.
◦
If set to 0, the SCL is held low until the next command is written to the transmit FIFO.
For more details, refer to Section 4.4.7.
4.4.6. I2C Protocols
The DW_apb_i2c has the protocols discussed in this section.
RP2040 Datasheet
4.4. I2C 467