Datasheet

bus and every device can talk with any master, passing information back and forth. There needs to be at least one master
(such as a microcontroller or DSP) on the bus but there can be multiple masters, which require them to arbitrate for
ownership. Multiple masters and arbitration are explained later in this chapter. The I2C block does not support SMBus and
PMBus protocols (for System Management and Power management).
The DW_apb_i2c is made up of an AMBA APB slave interface, an I2C interface, and FIFO logic to maintain coherency
between the two interfaces. The blocks of the component are illustrated in Figure 62.
AMBA Bus
Interface Unit
Register File
Slave State
Machine
Master State
Machine
Clock Generator Rx Shift Tx Shift Rx Filter
Toggle Synchronizer DMA Interface
Interrupt
Controller
RX FIFO TX FIFO
DW_apb_i2c
Figure 62. I2C Block
diagram
The following define the functions of the blocks in Figure 62:
•
AMBA Bus Interface Unit — Takes the APB interface signals and translates them into a common generic interface
that allows the register file to be bus protocol-agnostic.
•
Register File — Contains configuration registers and is the interface with software.
•
Slave State Machine — Follows the protocol for a slave and monitors bus for address match.
•
Master State Machine — Generates the I2C protocol for the master transfers.
•
Clock Generator — Calculates the required timing to do the following:
◦
Generate the SCL clock when configured as a master
◦
Check for bus idle
◦
Generate a START and a STOP
◦
Setup the data and hold the data
•
Rx Shift — Takes data into the design and extracts it in byte format.
•
Tx Shift — Presents data supplied by CPU for transfer on the I2C bus.
•
Rx Filter — Detects the events in the bus; for example, start, stop and arbitration lost.
•
Toggle — Generates pulses on both sides and toggles to transfer signals across clock domains.
•
Synchronizer — Transfers signals from one clock domain to another.
•
DMA Interface — Generates the handshaking signals to the central DMA controller in order to automate the data
transfer without CPU intervention.
•
Interrupt Controller — Generates the raw interrupt and interrupt flags, allowing them to be set and cleared.
•
RX FIFO/TX FIFO — Holds the RX FIFO and TX FIFO register banks and controllers, along with their status levels.
RP2040 Datasheet
4.4. I2C 465