Datasheet

•
Allows restart conditions when a master (can be disabled for legacy device support)
•
Configurable timing to adjust TsuDAT/ThDAT
•
General calls responded to on reset
•
Interface to DMA
•
Single interrupt output
•
Configurable timing to adjust clock frequency
•
Spike suppression (default 7 clk_sys cycles)
•
Can NACK after data received by Slave
•
Hold transfer when TX FIFO empty
•
Hold bus until space available in RX FIFO
•
Restart detect interrupt in Slave mode
•
Optional blocking Master commands (not enabled by default)
4.4.3. I2C Overview
The I2C bus is a 2-wire serial interface, consisting of a serial data line SDA and a serial clock SCL. These wires carry
information between the devices connected to the bus. Each device is recognized by a unique address and can operate as
either a “transmitter” or “receiver”, depending on the function of the device. Devices can also be considered as masters or
slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the
clock signals to permit that transfer. At that time, any device addressed is considered a slave.

NOTE
The I2C block must only be programmed to operate in either master OR slave mode only. Operating as a master and
slave simultaneously is not supported.
The I2C block can operate in these modes:
•
standard mode (with data rates from 0 to 100 Kb/s),
•
fast mode (with data rates less than or equal to 400 Kb/s),
•
fast mode plus (with data rates less than or equal to 1000 Kb/s).
These modes are not supported:
•
High-speed mode (with data rates less than or equal to 3.4 Mb/s),
•
Ultra-Fast Speed Mode (with data rates less than or equal to 5 Mb/s).

NOTE
References to fast mode also apply to fast mode plus, unless specifically stated otherwise.
The I2C block can communicate with devices in one of these modes as long as they are attached to the bus. Additionally,
fast mode devices are downward compatible. For instance, fast mode devices can communicate with standard mode
devices in 0 to 100 Kb/s I2C bus system. However standard mode devices are not upward compatible and should not be
incorporated in a fast-mode I2C bus system as they cannot follow the higher transfer rate and unpredictable states would
occur.
An example of high-speed mode devices are LCD displays, high-bit count ADCs, and high capacity EEPROMs. These
devices typically need to transfer large amounts of data. Most maintenance and control applications, the common use for
the I2C bus, typically operate at 100 kHz (in standard and fast modes). Any DW_apb_i2c device can be attached to an I2C-
RP2040 Datasheet
4.4. I2C 464