Datasheet

Bits Name Description Type Reset
1 SIREN SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT
remains LOW (no light pulse generated), and signal
transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is
enabled. Data is transmitted and received on nSIROUT and
SIRIN. UARTTXD remains HIGH, in the marking state.
Signal transitions on UARTRXD or modem status inputs
have no effect. This bit has no effect if the UARTEN bit
disables the UART.
RW 0x0
0 UARTEN UART enable: 0 = UART is disabled. If the UART is disabled
in the middle of transmission or reception, it completes the
current character before stopping. 1 = the UART is enabled.
Data transmission and reception occurs for either UART
signals or SIR signals depending on the setting of the
SIREN bit.
RW 0x0
UARTIFLS Register
Description
Interrupt FIFO Level Select Register, UARTIFLS
Table 462. UARTIFLS
Register
Bits Name Description Type Reset
31:6 Reserved. - - -
5:3 RXIFLSEL Receive interrupt FIFO level select. The trigger points for
the receive interrupt are as follows: b000 = Receive FIFO
becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 /
4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 =
Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO
becomes >= 7 / 8 full b101-b111 = reserved.
RW 0x2
2:0 TXIFLSEL Transmit interrupt FIFO level select. The trigger points for
the transmit interrupt are as follows: b000 = Transmit FIFO
becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1
/ 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 =
Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO
becomes <= 7 / 8 full b101-b111 = reserved.
RW 0x2
UARTIMSC Register
Description
Interrupt Mask Set/Clear Register, UARTIMSC
Table 463. UARTIMSC
Register
Bits Name Description Type Reset
31:11 Reserved. - - -
10 OEIM Overrun error interrupt mask. A read returns the current
mask for the UARTOEINTR interrupt. On a write of 1, the
mask of the UARTOEINTR interrupt is set. A write of 0
clears the mask.
RW 0x0
9 BEIM Break error interrupt mask. A read returns the current mask
for the UARTBEINTR interrupt. On a write of 1, the mask of
the UARTBEINTR interrupt is set. A write of 0 clears the
mask.
RW 0x0
RP2040 Datasheet
4.3. UART 457