Datasheet

Bits Name Description Type Reset
1 DSR Data set ready. This bit is the complement of the UART
data set ready, nUARTDSR, modem status input. That is,
the bit is 1 when nUARTDSR is LOW.
RO -
0 CTS Clear to send. This bit is the complement of the UART clear
to send, nUARTCTS, modem status input. That is, the bit is
1 when nUARTCTS is LOW.
RO -
UARTILPR Register
Description
IrDA Low-Power Counter Register, UARTILPR
Table 457. UARTILPR
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 ILPDVSR 8-bit low-power divisor value. These bits are cleared to 0 at
reset.
RW 0x00
UARTIBRD Register
Description
Integer Baud Rate Register, UARTIBRD
Table 458. UARTIBRD
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15:0 BAUD_DIVINT The integer baud rate divisor. These bits are cleared to 0 on
reset.
RW 0x0000
UARTFBRD Register
Description
Fractional Baud Rate Register, UARTFBRD
Table 459. UARTFBRD
Register
Bits Name Description Type Reset
31:6 Reserved. - - -
5:0 BAUD_DIVFRAC The fractional baud rate divisor. These bits are cleared to 0
on reset.
RW 0x00
UARTLCR_H Register
Description
Line Control Register, UARTLCR_H
Table 460.
UARTLCR_H Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7 SPS Stick parity select. 0 = stick parity is disabled 1 = either: * if
the EPS bit is 0 then the parity bit is transmitted and
checked as a 1 * if the EPS bit is 1 then the parity bit is
transmitted and checked as a 0. This bit has no effect
when the PEN bit disables parity checking and generation.
RW 0x0
RP2040 Datasheet
4.3. UART 454