Datasheet

Bits Name Description Type Reset
0 FE Framing error. When set to 1, it indicates that the received
character did not have a valid stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR. In FIFO
mode, this error is associated with the character at the top
of the FIFO.
WC 0x0
UARTFR Register
Description
Flag Register, UARTFR
Table 456. UARTFR
Register
Bits Name Description Type Reset
31:9 Reserved. - - -
8 RI Ring indicator. This bit is the complement of the UART ring
indicator, nUARTRI, modem status input. That is, the bit is 1
when nUARTRI is LOW.
RO -
7 TXFE Transmit FIFO empty. The meaning of this bit depends on
the state of the FEN bit in the Line Control Register,
UARTLCR_H. If the FIFO is disabled, this bit is set when the
transmit holding register is empty. If the FIFO is enabled,
the TXFE bit is set when the transmit FIFO is empty. This
bit does not indicate if there is data in the transmit shift
register.
RO 0x1
6 RXFF Receive FIFO full. The meaning of this bit depends on the
state of the FEN bit in the UARTLCR_H Register. If the FIFO
is disabled, this bit is set when the receive holding register
is full. If the FIFO is enabled, the RXFF bit is set when the
receive FIFO is full.
RO 0x0
5 TXFF Transmit FIFO full. The meaning of this bit depends on the
state of the FEN bit in the UARTLCR_H Register. If the FIFO
is disabled, this bit is set when the transmit holding register
is full. If the FIFO is enabled, the TXFF bit is set when the
transmit FIFO is full.
RO 0x0
4 RXFE Receive FIFO empty. The meaning of this bit depends on
the state of the FEN bit in the UARTLCR_H Register. If the
FIFO is disabled, this bit is set when the receive holding
register is empty. If the FIFO is enabled, the RXFE bit is set
when the receive FIFO is empty.
RO 0x1
3 BUSY UART busy. If this bit is set to 1, the UART is busy
transmitting data. This bit remains set until the complete
byte, including all the stop bits, has been sent from the shift
register. This bit is set as soon as the transmit FIFO
becomes non-empty, regardless of whether the UART is
enabled or not.
RO 0x0
2 DCD Data carrier detect. This bit is the complement of the UART
data carrier detect, nUARTDCD, modem status input. That
is, the bit is 1 when nUARTDCD is LOW.
RO -
RP2040 Datasheet
4.3. UART 453