Datasheet

FIFO trigger levels.
The error interrupt, UARTEINTR, can be triggered when there is an error in the reception of data. A number of error
conditions are possible.
The modem status interrupt, UARTMSINTR, is a combined interrupt of all the individual modem status signals.
The status of the individual interrupt sources can be read either from the Raw Interrupt Status Register, UARTRIS, or from
the Masked Interrupt Status Register, UARTMIS.
4.3.6.1. UARTMSINTR
The modem status interrupt is asserted if any of the modem status signals (nUARTCTS, nUARTDCD, nUARTDSR, and
nUARTRI) change. It is cleared by writing a 1 to the corresponding bit(s) in the Interrupt Clear Register, UARTICR,
depending on the modem status signals that generated the interrupt.
4.3.6.2. UARTRXINTR
The receive interrupt changes state when one of the following events occurs:
•
If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level. When this happens, the receive
interrupt is asserted HIGH. The receive interrupt is cleared by reading data from the receive FIFO until it becomes
less than the trigger level, or by clearing the interrupt.
•
If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the location, the receive
interrupt is asserted HIGH. The receive interrupt is cleared by performing a single read of the receive FIFO, or by
clearing the interrupt.
4.3.6.3. UARTTXINTR
The transmit interrupt changes state when one of the following events occurs:
•
If the FIFOs are enabled and the transmit FIFO is equal to or lower than the programmed trigger level then the
transmit interrupt is asserted HIGH. The transmit interrupt is cleared by writing data to the transmit FIFO until it
becomes greater than the trigger level, or by clearing the interrupt.
•
If the FIFOs are disabled (have a depth of one location) and there is no data present in the transmitters single
location, the transmit interrupt is asserted HIGH. It is cleared by performing a single write to the transmit FIFO, or by
clearing the interrupt.
To update the transmit FIFO you must:
•
Write data to the transmit FIFO, either prior to enabling the UART and the interrupts, or after enabling the UART and
interrupts.

NOTE
The transmit interrupt is based on a transition through a level, rather than on the level itself. When the interrupt and the
UART is enabled before any data is written to the transmit FIFO the interrupt is not set. The interrupt is only set, after
written data leaves the single location of the transmit FIFO and it becomes empty.
4.3.6.4. UARTRTINTR
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no more data is received during a 32-bit
period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by
reading the holding register), or when a 1 is written to the corresponding bit of the Interrupt Clear Register, UARTICR.
RP2040 Datasheet
4.3. UART 448