Datasheet

Table Of Contents
Stop
Stop bit
TXD
DMASREQ
DMABREQ
DMACLR
Start bit
Bit period
Start
Bit period
0
0 1 0 1 0 0 1 1 0 1
1 0 1 0 1 1 0 10
Data bits
Data bits
3/16
Figure 59. UART
character frame.
4.3.4. UART hardware flow control
The hardware flow control feature is fully selectable, and enables you to control the serial data flow by using the
nUARTRTS output and nUARTCTS input signals. Figure 60 shows how two devices can communicate with each other
using hardware flow control.
Figure 60. Hardware
flow control between
two similar devices.
When the RTS flow control is enabled, nUARTRTS is asserted until the receive FIFO is filled up to the programmed
watermark level. When the CTS flow control is enabled, the transmitter can only transmit data when nUARTCTS is
asserted.
The hardware flow control is selectable using the RTSEn and CTSEn bits in the Control Register, UARTCR. Table 451 lists
how you must set the bits to enable RTS and CTS flow control both simultaneously, and independently.
Table 451. Control bits
to enable and disable
hardware flow control.
UARTCR Register bits
CTSEn RTSEn Description
1 1 Both RTS and CTS flow control
enabled
1 0 Only CTS flow control enabled
0 1 Only RTS flow control enabled
0 0 Both RTS and CTS flow control
disabled
NOTE
When RTS flow control is enabled, the software cannot use the RTSEn bit in the Control Register, UARTCR, to control
the status of nUARTRTS.
4.3.4.1. RTS flow control
The RTS flow control logic is linked to the programmable receive FIFO watermark levels. When RTS flow control is
enabled, the nUARTRTS is asserted until the receive FIFO is filled up to the watermark level. When the receive FIFO
watermark level is reached, the nUARTRTS signal is deasserted, indicating that there is no more room to receive any more
data. The transmission of data is expected to cease after the current character has been transmitted.
RP2040 Datasheet
4.3. UART 445