Datasheet

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Received data rx (referred to as UARTRXD in the following sections)
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Output flow control rts (referred to as nUARTRTS in the following sections)
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Input flow control cts (referred to as nUARTCTS in the following sections)
The modem mode and IrDA mode of the PL011 are not supported.
The UARTCLK is driven from clk_peri, and PCLK is driven from the system clock clk_sys (see Figure 26).
4.3.1. Overview
The UART performs:
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serial-to-parallel conversion on data received from a peripheral device
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parallel-to-serial conversion on data transmitted to the peripheral device.
The CPU reads and writes data and control/status information through the AMBA APB interface. The transmit and receive
paths are buffered with internal FIFO memories enabling up to 32-bytes to be stored independently in both transmit and
receive modes.
The UART:
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includes a programmable baud rate generator that generates a common transmit and receive internal clock from the
UART internal reference clock input, UARTCLK
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offers similar functionality to the industry-standard 16C650 UART device
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supports the a maximum baud rates of 921600 bps in UART mode
The UART operation and baud rate values are controlled by the Line Control Register, UARTLCR_H and the baud rate
divisor registers (Integer Baud Rate Register, UARTIBRD and Fractional Baud Rate Register, UARTFBRD).
The UART can generate:
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individually-maskable interrupts from the receive (including timeout), transmit, modem status and error conditions
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a single combined interrupt so that the output is asserted if any of the individual interrupts are asserted, and
unmasked
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DMA request signals for interfacing with a Direct Memory Access (DMA) controller.
If a framing, parity, or break error occurs during reception, the appropriate error bit is set, and is stored in the FIFO. If an
overrun condition occurs, the overrun register bit is set immediately and FIFO data is prevented from being overwritten.
You can program the FIFOs to be 1-byte deep providing a conventional double-buffered UART interface.
There is a programmable hardware flow control feature that uses the nUARTCTS input and the nUARTRTS output to
automatically control the serial data flow.
4.3.2. Functional description
RP2040 Datasheet
4.3. UART 440