Datasheet

Table 447.
N_CHANNELS Register
Bits Name Description Type Reset
31:5 Reserved. - - -
4:0 NONAME The number of channels this DMA instance is equipped
with. This DMA supports up to 16 hardware channels, but
can be configured with as few as one, to minimise silicon
area.
RO -
CH0_DBG_CTDREQ, CH1_DBG_CTDREQ, …, CH10_DBG_CTDREQ,
CH11_DBG_CTDREQ Registers
Table 448.
CH0_DBG_CTDREQ,
CH1_DBG_CTDREQ, …,
CH10_DBG_CTDREQ,
CH11_DBG_CTDREQ
Registers
Bits Name Description Type Reset
31:6 Reserved. - - -
5:0 NONAME Read: get channel DREQ counter (i.e. how many accesses
the DMA expects it can perform on the peripheral without
overflow/underflow. Write any value: clears the counter,
and cause channel to re-initiate DREQ handshake.
RO 0x00
CH0_DBG_TCR, CH1_DBG_TCR, …, CH10_DBG_TCR, CH11_DBG_TCR Registers
Description
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Table 449.
CH0_DBG_TCR,
CH1_DBG_TCR, …,
CH10_DBG_TCR,
CH11_DBG_TCR
Registers
Bits Name Description Type Reset
31:0 NONAME RO 0x00000000
4.3. UART
ARM Documentation
Excerpted from the PrimeCell UART (PL011) Technical Reference Manual. Used with permission.
RP2040 has 2 identical instances of a UART peripheral, based on the ARM Primecell UART (PL011) (Revision r1p5).
Each instance supports the following features:
•
Separate 32x8 Tx and 32x12 Rx FIFOs
•
Programmable baud rate generator, clocked by clk_peri (see Figure 26)
•
Standard asynchronous communication bits (start, stop, parity) added on transmit and removed on receive
•
line break detection
•
programmable serial interface (5, 6, 7, or 8 bits)
•
1 or 2 stop bits
•
programmable hardware flow control
Each UART can be connected to a number of GPIO pins as defined in the GPIO muxing table in Section 2.18.2.
Connections to the GPIO muxing are prefixed with the UART instance name uart0_ or uart1_, and include the following:
•
Transmit data tx (referred to as UARTTXD in the following sections)
RP2040 Datasheet
4.3. UART 439