Datasheet

Bits Name Description Type Reset
0 EN Enable sniffer RW 0x0
SNIFF_DATA Register
Description
Data accumulator for sniff hardware
Table 444.
SNIFF_DATA Register
Bits Name Description Type Reset
31:0 NONAME Write an initial seed value here before starting a DMA
transfer on the channel indicated by SNIFF_CTRL_DMACH.
The hardware will update this register each time it
observes a read from the indicated channel. Once the
channel completes, the final result can be read from this
register.
RW 0x00000000
FIFO_LEVELS Register
Description
Debug RAF, WAF, TDF levels
Table 445.
FIFO_LEVELS Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:16 RAF_LVL Current Read-Address-FIFO fill level RO 0x00
15:8 WAF_LVL Current Write-Address-FIFO fill level RO 0x00
7:0 TDF_LVL Current Transfer-Data-FIFO fill level RO 0x00
CHAN_ABORT Register
Description
Abort an in-progress transfer sequence on one or more channels
Table 446.
CHAN_ABORT
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15:0 NONAME Each bit corresponds to a channel. Writing a 1 aborts
whatever transfer sequence is in progress on that channel.
The bit will remain high until any in-flight transfers have
been flushed through the address and data FIFOs.
After writing, this register must be polled until it returns all-
zero. Until this point, it is unsafe to restart the channel.
SC 0x0000
N_CHANNELS Register
RP2040 Datasheet
4.2. DMA 438