Datasheet

Table 441. TIMER0,
TIMER1 Registers
Bits Name Description Type Reset
31:16 X Pacing Timer Dividend. Specifies the X value for the (X/Y)
fractional timer.
RW 0x0000
15:0 Y Pacing Timer Divisor. Specifies the Y value for the (X/Y)
fractional timer.
RW 0x0000
MULTI_CHAN_TRIGGER Register
Description
Trigger one or more channels simultaneously
Table 442.
MULTI_CHAN_TRIGGE
R Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15:0 NONAME Each bit in this register corresponds to a DMA channel.
Writing a 1 to the relevant bit is the same as writing to that
channel’s trigger register; the channel will start if it is
currently enabled and not already busy.
SC 0x0000
SNIFF_CTRL Register
Description
Sniffer Control
Table 443.
SNIFF_CTRL Register
Bits Name Description Type Reset
31:12 Reserved. - - -
11 OUT_INV If set, the result appears inverted (bitwise complement)
when read. This does not affect the way the checksum is
calculated; the result is transformed on-the-fly between the
result register and the bus.
RW 0x0
10 OUT_REV If set, the result appears bit-reversed when read. This does
not affect the way the checksum is calculated; the result is
transformed on-the-fly between the result register and the
bus.
RW 0x0
9 BSWAP Locally perform a byte reverse on the sniffed data, before
feeding into checksum.
Note that the sniff hardware is downstream of the DMA
channel byteswap performed in the read master: if channel
CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled,
their effects cancel from the sniffer’s point of view.
RW 0x0
8:5 CALC 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial)
0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit
reversed data
0x2 -> Calculate a CRC-16-CCITT
0x3 -> Calculate a CRC-16-CCITT with bit reversed data
0xe -> XOR reduction over all data. == 1 if the total 1
population count is odd.
0xf -> Calculate a simple 32-bit checksum (addition with a
32 bit accumulator)
RW 0x0
4:1 DMACH DMA channel for Sniffer to observe RW 0x0
RP2040 Datasheet
4.2. DMA 437