Datasheet

Bits Name Description Type Reset
1 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in
issue scheduling: in each scheduling round, all high priority
channels are considered first, and then only a single low
priority channel, before returning to the high priority
channels.
This only affects the order in which the DMA schedules
channels. The DMA’s bus priority is not changed. If the
DMA is not saturated then a low priority channel will see no
loss of throughput.
RW 0x0
0 EN DMA Channel Enable.
When 1, the channel will respond to triggering events,
which will cause it to become BUSY and start transferring
data. When 0, the channel will ignore triggers, stop issuing
transfers, and pause the current transfer sequence (i.e.
BUSY will remain high if already high)
RW 0x0
CH0_AL1_CTRL, CH1_AL1_CTRL, …, CH10_AL1_CTRL, CH11_AL1_CTRL
Registers
Description
Alias for channel N CTRL register
Table 422.
CH0_AL1_CTRL,
CH1_AL1_CTRL, …,
CH10_AL1_CTRL,
CH11_AL1_CTRL
Registers
Bits Name Description Type Reset
31:0 NONAME RO -
CH0_AL1_READ_ADDR, CH1_AL1_READ_ADDR, …, CH10_AL1_READ_ADDR,
CH11_AL1_READ_ADDR Registers
Description
Alias for channel N READ_ADDR register
Table 423.
CH0_AL1_READ_ADDR
,
CH1_AL1_READ_ADDR
, …,
CH10_AL1_READ_ADD
R,
CH11_AL1_READ_ADD
R Registers
Bits Name Description Type Reset
31:0 NONAME RO -
CH0_AL1_WRITE_ADDR, CH1_AL1_WRITE_ADDR, …, CH10_AL1_WRITE_ADDR,
CH11_AL1_WRITE_ADDR Registers
Description
Alias for channel N WRITE_ADDR register
Table 424.
CH0_AL1_WRITE_ADD
R,
CH1_AL1_WRITE_ADD
R, …,
CH10_AL1_WRITE_AD
DR,
CH11_AL1_WRITE_AD
DR Registers
Bits Name Description Type Reset
31:0 NONAME RO -
CH0_AL1_TRANS_COUNT_TRIG, CH1_AL1_TRANS_COUNT_TRIG, …,
CH10_AL1_TRANS_COUNT_TRIG, CH11_AL1_TRANS_COUNT_TRIG Registers
Description
Alias for channel N TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
RP2040 Datasheet
4.2. DMA 432